feat(cpu): retain ARM instruction pipeline words

Buffer ARM sequential fetch results and refill target pairs after branches, PC writes, and machine exception entry. Stage advances transactionally, defer speculative fetch diagnostics, and preserve buffered words across CPU/DMA stores and host edits. Add explicit CPU pipeline invalidation for debugger repair and memory rebinding.

Add 15 original instruction-buffer regressions. Keep full-state rollback equality while distinguishing architectural comparisons in semantic tests. Update the display error test for an already buffered branch. Document evidence and separate remaining Thumb, bus-history, and timing work.

Validated on Darwin arm64: 967 workspace and 898 core/demo tests in each debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports and nominal cycles remain unchanged.

crates/gba-core/tests/display.rs

@@ -444,6 +444,11 @@ fn frame_runner_limits_and_cpu_errors_preserve_completed_progress_only() {
         machine.run_until_vblank(10),
         Err(FrameRunError::Cpu(_))
     ));
-    assert_eq!(machine.memory().display_position(), position);
-    assert_eq!(machine.cycles(), 6);
+    // The already buffered branch executes once and refills from the patched word.
+    // The unsupported instruction then fails without further device progress.
+    assert_eq!(
+        machine.memory().display_position().line_cycle,
+        position.line_cycle + 3
+    );
+    assert_eq!(machine.cycles(), 9);
 }