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fix(cpu): store PC plus six for Thumb empty register lists

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Correct the shared Thumb block-store PC offset from four to six bytes. Retain ARM PC+12, 64-byte empty-list writeback, normal load behavior, alignment, flags, and nominal timing. Correct prior internal expectations and add original regressions for bases, banks, alignment, ROM windows, writeback, clocks, and atomic errors.

The pinned public Thumb ROM now passes its unchanged ARM-state r7 checkpoint after 807 steps and 4170 nominal cycles. The pinned ARM ROM still passes. Neither external ROM nor result assertion is modified.

Validated on Darwin arm64: 848 workspace tests in debug and release; 779 core/demo tests separately; 21 Python adapter tests; both public suites in both profiles; native ROM-window tests; all ten demo window smoke tests; fmt, clippy, rustdoc, and local documentation links.
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0xrsydn 2026-10-05 20:47:20 +07:00
commit 3d67b136ba
12 changed files with 222 additions and 17 deletions
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docs/public-thumb-tests.md
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@ -1,7 +1,7 @@
# Pinned public Thumb test
The headless runner executes the unmodified Thumb ROM from [jsmolka/gba-tests](https://github.com/jsmolka/gba-tests).
It currently reaches its result checkpoint but fails test 229 on Darwin arm64 in debug and release builds.
It now passes its result checkpoint on Darwin arm64 in debug and release builds. The initial test 229 failure is retained below.
This is an independent compatibility baseline, not complete ARM7TDMI conformance or a hardware measurement.
## Prepare and run
@ -67,8 +67,20 @@ Initial integration, before fixing empty-list Thumb stores:
- The stored PC value is `0x080008be`, but the following PC read expects `0x080008c0`.
- The public ARM ROM still passes its unchanged checkpoint.
The next CPU task is to verify the empty-list store PC offset and correct it with original regressions.
Do not change the pinned ROM or weaken the result assertion to pass this test.
After correcting the empty-list store PC offset:
- Thumb empty-list stores use executing PC+6 instead of PC+4. ARM stores retain PC+12.
- Test 229 and the later memory tests complete without taking their failure paths.
- The runner reaches `0x08000934` after 807 successful steps and 4,170 nominal cycles.
- The CPU is in System/ARM state with CPSR `0x0000001f` and r7 = 0.
- Debug and release builds exit zero with `reason: checkpoint`, no error, and the result assertion passing.
- Both public ROMs pass with their original bytes, checkpoint addresses, budgets, and assertions unchanged.
Original regressions reproduce the stored-PC mismatch without public ROM bytes.
They cover all low base registers, banked stack pointers, code/data alignment, ROM windows, timing, and atomic diagnostics.
Existing empty-list expectations that incorrectly required PC+4 were corrected; empty loads and ARM stores retain their behavior.
See [CPU transfer semantics](hardware/cpu.md#instruction-demo-and-execution-rules).
This proves only the pinned suites' checkpoints and assertions, not complete CPU, bus, or timing compatibility.
No public timing, memory, BIOS, graphics, or unsafe suite is claimed as passing.
These results do not establish Pokémon Emerald compatibility.