fix(cpu): store PC plus six for Thumb empty register lists
Correct the shared Thumb block-store PC offset from four to six bytes. Retain ARM PC+12, 64-byte empty-list writeback, normal load behavior, alignment, flags, and nominal timing. Correct prior internal expectations and add original regressions for bases, banks, alignment, ROM windows, writeback, clocks, and atomic errors. The pinned public Thumb ROM now passes its unchanged ARM-state r7 checkpoint after 807 steps and 4170 nominal cycles. The pinned ARM ROM still passes. Neither external ROM nor result assertion is modified. Validated on Darwin arm64: 848 workspace tests in debug and release; 779 core/demo tests separately; 21 Python adapter tests; both public suites in both profiles; native ROM-window tests; all ten demo window smoke tests; fmt, clippy, rustdoc, and local documentation links.
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@ -110,7 +110,8 @@ Test 362 checks shifted addressing, writeback, and carry, but does not check the
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Original regressions separately check the returned word, byte lanes, rotation, sign extension, timing, and retained diagnostics.
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See the bounded [ARM open-bus implementation](hardware/cpu.md#arm-unused-memory-data-reads).
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This is a passing result for this pinned ARM ROM, not proof of complete instruction, memory, or timing compatibility.
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No public Thumb, timing, memory, BIOS, graphics, or unsafe suite has been claimed as passing.
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The [pinned public Thumb ROM](public-thumb-tests.md) also passes its verified checkpoint.
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No public timing, memory, BIOS, graphics, or unsafe suite has been claimed as passing.
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These results do not establish Pokémon Emerald compatibility.
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## References
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