feat(cartridge): add 32 KiB SRAM save memory
Select it with --save-type sram (SaveDevice::Sram). The array is byte-wide, starts erased, and repeats every 32 KiB through the 0x0e00xxxx save window. A CPU byte store is staged and committed when its step completes, so failed steps roll back and reads later in the step see the byte. Unlike Flash, SRAM can be read from ROM code. Halfword/word access and DMA stay diagnostic until the 8-bit bus behavior for those widths is verified. SRAM shares the save-image API, host save files, and save states. Its device code is new, so existing save states keep loading. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HhfHfHEuzv2AUTd6erW1gU
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20176716d9
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15 changed files with 405 additions and 30 deletions
128
crates/gba-core/src/cartridge/sram.rs
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128
crates/gba-core/src/cartridge/sram.rs
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//! Battery-backed SRAM: a 32 KiB byte-wide array with no command protocol.
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//! A CPU byte store is staged as a one-byte mutation and committed when its step completes.
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//! Halfword and word accesses remain diagnostic until their 8-bit bus behavior is verified.
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use super::{SaveDevice, SaveMutation, SAVE_START};
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use crate::memory::MemoryError;
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use crate::snapshot::{Reader, Snapshot, SnapshotError, Writer};
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/// The 32 KiB array repeats through the 64 KiB save window.
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const MIRROR_MASK: u32 = 0x7fff;
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub(super) struct Sram {
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pending: Option<SaveMutation>,
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}
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impl Sram {
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fn index(address: u32) -> usize {
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((address - SAVE_START) & MIRROR_MASK) as usize
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}
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pub(super) fn read(self, address: u32, image: &[u8]) -> u8 {
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let index = Self::index(address);
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match self.pending {
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Some(mutation) if (mutation.start..mutation.end).contains(&index) => mutation.value,
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_ => image[index],
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}
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}
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pub(super) fn write(&mut self, address: u32, value: u8) -> Result<(), MemoryError> {
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if self.pending.is_some() {
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// One CPU step performs at most one byte store; DMA cannot write bytes.
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "second SRAM write before commit",
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});
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}
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let start = Self::index(address);
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self.pending = Some(SaveMutation {
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start,
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end: start + 1,
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value,
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});
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Ok(())
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}
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pub(super) fn unfinished(self) -> bool {
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self.pending.is_some()
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}
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pub(super) fn take_mutation(&mut self) -> Option<SaveMutation> {
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self.pending.take()
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}
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}
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impl Snapshot for Sram {
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fn save(&self, writer: &mut Writer) {
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let Self { pending } = self;
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writer.tag(b"SRAM");
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writer.option(pending.as_ref(), |pending, writer| pending.save(writer));
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}
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fn load(&mut self, reader: &mut Reader<'_>) -> Result<(), SnapshotError> {
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let Self { pending } = self;
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reader.tag(b"SRAM")?;
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let decoded = reader.option(|reader| {
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let mut mutation = SaveMutation {
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start: 0,
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end: 0,
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value: 0,
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};
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mutation.load(reader)?;
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Ok(mutation)
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})?;
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if decoded.is_some_and(|m| m.end != m.start + 1 || m.end > SaveDevice::Sram.capacity()) {
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return Err(SnapshotError::Corrupt("SRAM mutation range"));
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}
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*pending = decoded;
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Ok(())
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn writes_stage_one_mirrored_byte_and_reads_see_it_before_commit() {
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let image = vec![0xff; SaveDevice::Sram.capacity()];
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let mut sram = Sram::default();
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sram.write(SAVE_START + 0x8001, 0x42).unwrap(); // Mirror of offset 1.
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assert_eq!(sram.read(SAVE_START + 1, &image), 0x42);
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assert_eq!(sram.read(SAVE_START + 0x8001, &image), 0x42);
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assert_eq!(sram.read(SAVE_START, &image), 0xff);
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assert!(sram.unfinished());
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assert!(sram.write(SAVE_START, 0).is_err());
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let mutation = sram.take_mutation().unwrap();
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assert_eq!((mutation.start, mutation.end, mutation.value), (1, 2, 0x42));
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assert!(!sram.unfinished());
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}
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#[test]
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fn snapshot_round_trips_and_rejects_out_of_range_mutations() {
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let mut sram = Sram::default();
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sram.write(SAVE_START + 0x7fff, 7).unwrap();
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let mut writer = Writer::new();
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sram.save(&mut writer);
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let bytes = writer.finish().unwrap();
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let mut restored = Sram::default();
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restored.load(&mut Reader::new(&bytes)).unwrap();
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assert_eq!(restored, sram);
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let mut writer = Writer::new();
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Sram {
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pending: Some(SaveMutation {
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start: 0x8000,
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end: 0x8001,
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value: 0,
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}),
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}
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.save(&mut writer);
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let bytes = writer.finish().unwrap();
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assert_eq!(
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Sram::default().load(&mut Reader::new(&bytes)),
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Err(SnapshotError::Corrupt("SRAM mutation range"))
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);
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}
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}
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