0xrsydn/gameboy-rust
1
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

feat(cpu): account for source fetches in branch and IRQ refills

Browse source
This commit is contained in:
0xrsydn 2026-10-06 16:27:45 +07:00
commit 2d7eb6e4eb
27 changed files with 638 additions and 87 deletions
Download patch file Download diff file Expand all files Collapse all files

9
crates/gba-core/tests/timing.rs
View file

@ -128,8 +128,11 @@ fn stored_prefetch_phi_and_sram_settings_do_not_change_supported_bus_costs() {
#[test]
fn wait_states_change_when_a_timer_interrupt_is_sampled() {
// 20-cycle timer: four 6-cycle fetches or five 4-cycle fetches, then 3-cycle IRQ entry.
for (waitcnt, entry_step, instructions, cycles) in [(0, 5, 4, 27), (0x18, 6, 5, 23)] {
// 20-cycle timer: four 6-cycle fetches or five 4-cycle fetches.
// IRQ entry adds one old-state ROM fetch and the two-cycle BIOS vector pair.
for (waitcnt, entry_step, instructions, cycles, irq_cycles) in
[(0, 5, 4, 32, 8), (0x18, 6, 5, 26, 6)]
{
let mut memory = Memory::new(0xe280_0001_u32.to_le_bytes().repeat(64)).unwrap();
memory.write16(WAITCNT, waitcnt).unwrap();
memory.write32(TIMER_BASE, 0x00c0_ffec).unwrap(); // 20 cycles
@ -150,7 +153,7 @@ fn wait_states_change_when_a_timer_interrupt_is_sampled() {
}
assert_eq!(machine.cpu().registers()[0], instructions);
assert_eq!(machine.cycles(), cycles);
assert_eq!(machine.last_timing().code_cycles, 3);
assert_eq!(machine.last_timing().code_cycles, irq_cycles);
}
}