feat(cpu): account for source fetches in branch and IRQ refills
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parent
0650b60908
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2d7eb6e4eb
27 changed files with 638 additions and 87 deletions
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@ -65,7 +65,8 @@ fn timer_demo_configures_hardware_in_cpu_code_and_handles_exactly_one_irq() {
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assert_eq!(machine.cpu().registers()[10], 1);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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assert_eq!(machine.memory().read16(TIMER_BASE + 2).unwrap(), 0);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xfff4);
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// IRQ entry gains five cycles before the timer stops; return loses five afterward.
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xfff9);
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for _ in 0..100 {
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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}
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@ -84,7 +85,7 @@ fn overflow_after_instruction_is_sampled_on_next_step() {
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.cpu().registers()[0], 1); // Interrupted instruction did not execute
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assert_eq!(machine.cpu().registers()[14], ROM_START + 8);
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assert_eq!(machine.cycles(), 9); // New ROM fetch at PC+8: 6; nominal BIOS IRQ refill: 3
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assert_eq!(machine.cycles(), 14); // Instruction fetch 6; IRQ source fetch 6 + BIOS pair 2.
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}
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#[test]
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@ -92,7 +93,7 @@ fn missing_vector_errors_only_after_completed_irq_entry() {
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let mut bus = Memory::new(vec![]).unwrap();
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pending_timer(&mut bus);
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry); // No ROM fetch required
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry); // Missing discarded ROM fetch cannot prevent IRQ entry
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let before = machine.cpu().clone();
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let cycles = machine.cycles();
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assert_eq!(
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