0xrsydn/gameboy-rust
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feat(cpu): account for source fetches in branch and IRQ refills

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0xrsydn 2026-10-06 16:27:45 +07:00
commit 2d7eb6e4eb
27 changed files with 638 additions and 87 deletions
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7
crates/gba-core/tests/machine.rs
View file

@ -65,7 +65,8 @@ fn timer_demo_configures_hardware_in_cpu_code_and_handles_exactly_one_irq() {
assert_eq!(machine.cpu().registers()[10], 1);
assert_eq!(machine.memory().read16(IF).unwrap(), 0);
assert_eq!(machine.memory().read16(TIMER_BASE + 2).unwrap(), 0);
assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xfff4);
// IRQ entry gains five cycles before the timer stops; return loses five afterward.
assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xfff9);
for _ in 0..100 {
assert_eq!(machine.step().unwrap(), StepKind::Instruction);
}
@ -84,7 +85,7 @@ fn overflow_after_instruction_is_sampled_on_next_step() {
assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
assert_eq!(machine.cpu().registers()[0], 1); // Interrupted instruction did not execute
assert_eq!(machine.cpu().registers()[14], ROM_START + 8);
assert_eq!(machine.cycles(), 9); // New ROM fetch at PC+8: 6; nominal BIOS IRQ refill: 3
assert_eq!(machine.cycles(), 14); // Instruction fetch 6; IRQ source fetch 6 + BIOS pair 2.
}
#[test]
@ -92,7 +93,7 @@ fn missing_vector_errors_only_after_completed_irq_entry() {
let mut bus = Memory::new(vec![]).unwrap();
pending_timer(&mut bus);
let mut machine = Machine::new(Cpu::new(ROM_START), bus);
assert_eq!(machine.step().unwrap(), StepKind::IrqEntry); // No ROM fetch required
assert_eq!(machine.step().unwrap(), StepKind::IrqEntry); // Missing discarded ROM fetch cannot prevent IRQ entry
let before = machine.cpu().clone();
let cycles = machine.cycles();
assert_eq!(

9
crates/gba-core/tests/timing.rs
View file

@ -128,8 +128,11 @@ fn stored_prefetch_phi_and_sram_settings_do_not_change_supported_bus_costs() {
#[test]
fn wait_states_change_when_a_timer_interrupt_is_sampled() {
// 20-cycle timer: four 6-cycle fetches or five 4-cycle fetches, then 3-cycle IRQ entry.
for (waitcnt, entry_step, instructions, cycles) in [(0, 5, 4, 27), (0x18, 6, 5, 23)] {
// 20-cycle timer: four 6-cycle fetches or five 4-cycle fetches.
// IRQ entry adds one old-state ROM fetch and the two-cycle BIOS vector pair.
for (waitcnt, entry_step, instructions, cycles, irq_cycles) in
[(0, 5, 4, 32, 8), (0x18, 6, 5, 26, 6)]
{
let mut memory = Memory::new(0xe280_0001_u32.to_le_bytes().repeat(64)).unwrap();
memory.write16(WAITCNT, waitcnt).unwrap();
memory.write32(TIMER_BASE, 0x00c0_ffec).unwrap(); // 20 cycles
@ -150,7 +153,7 @@ fn wait_states_change_when_a_timer_interrupt_is_sampled() {
}
assert_eq!(machine.cpu().registers()[0], instructions);
assert_eq!(machine.cycles(), cycles);
assert_eq!(machine.last_timing().code_cycles, 3);
assert_eq!(machine.last_timing().code_cycles, irq_cycles);
}
}