fix(timers): retain shared free-running prescaler phase
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bfecc87e84
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27806ccf9e
13 changed files with 459 additions and 32 deletions
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@ -100,7 +100,7 @@ fn all_prescalers_retain_fractional_cycles_between_advances() {
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}
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#[test]
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fn clock_source_changes_and_restart_reset_provisional_phase() {
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fn clock_source_changes_and_restart_keep_the_shared_phase() {
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let mut bus = memory();
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bus.write32(TIMER_BASE, 0x0081_0000).unwrap(); // /64
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bus.advance_cycles(63);
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@ -108,16 +108,17 @@ fn clock_source_changes_and_restart_reset_provisional_phase() {
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bus.advance_cycles(1);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 1);
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bus.advance_cycles(63);
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bus.write16(TIMER_BASE + 2, 0x82).unwrap(); // /256 resets phase
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bus.advance_cycles(255);
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bus.write16(TIMER_BASE + 2, 0x82).unwrap(); // t=127: next shared /256 edge is t=256.
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bus.advance_cycles(128);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 1);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 2);
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bus.write16(TIMER_BASE + 2, 0).unwrap();
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bus.advance_cycles(255);
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bus.advance_cycles(255); // t=511; disabled time still advances the divider.
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bus.write16(TIMER_BASE + 2, 0x82).unwrap();
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bus.advance_cycles(255);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 1);
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}
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#[test]
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