fix(timers): retain shared free-running prescaler phase
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0xrsydn
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bfecc87e84
commit
27806ccf9e
13 changed files with 459 additions and 32 deletions
230
crates/gba-core/tests/timer_prescaler.rs
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230
crates/gba-core/tests/timer_prescaler.rs
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@ -0,0 +1,230 @@
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//! Original shared-divider checks. Startup and register-write delays remain outside this model.
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use gba_core::{
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cpu::Cpu,
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input::Buttons,
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io::{HALTCNT, IE, IF, KEYCNT, TIMER_BASE},
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machine::{Machine, StepKind},
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memory::{Memory, ROM_START},
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};
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const DIVISORS: [u64; 4] = [1, 64, 256, 1024];
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fn start(memory: &mut Memory, timer: u32, reload: u16, control: u16) {
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memory
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.write32(
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TIMER_BASE + timer * 4,
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u32::from(reload) | u32::from(control) << 16,
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)
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.unwrap();
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}
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#[test]
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fn every_shared_phase_selects_the_next_edge_without_replaying_the_current_edge() {
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for phase in 0..1024_u32 {
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let mut memory = Memory::new(Vec::new()).unwrap();
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memory.advance_cycles(phase); // The divider runs with all timers disabled.
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for selection in 0..4 {
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start(&mut memory, selection, 0, 0x80 | selection as u16);
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}
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memory.advance_cycles(0);
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for selection in 0..4 {
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assert_eq!(memory.read16(TIMER_BASE + selection * 4).unwrap(), 0);
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}
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// Cover two complete divider periods after every possible enable phase.
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let mut elapsed = 0;
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for delta in [1, 62, 1, 191, 1, 767, 1, 1024] {
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memory.advance_cycles(delta);
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elapsed += delta;
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for (selection, divisor) in DIVISORS.into_iter().enumerate() {
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let expected = (u64::from(phase + elapsed) / divisor) - u64::from(phase) / divisor;
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assert_eq!(
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memory.read16(TIMER_BASE + selection as u32 * 4).unwrap(),
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expected as u16,
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"phase={phase}, elapsed={elapsed}, divisor={divisor}"
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);
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}
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}
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}
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}
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#[test]
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fn staggered_timers_share_ticks_and_cascade_ignores_prescaler_selection() {
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let mut memory = Memory::new(Vec::new()).unwrap();
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memory.advance_cycles(10);
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start(&mut memory, 0, 0xfffe, 0xc1);
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memory.advance_cycles(15);
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start(&mut memory, 1, 0xfffe, 0xc1);
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memory.advance_cycles(38);
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start(&mut memory, 2, 0xfffe, 0xc1);
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start(&mut memory, 3, 0xffff, 0xc7); // Cascaded, /1024 field ignored.
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memory.advance_cycles(1); // All independent timers tick at system cycle 64.
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for index in 0..3 {
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assert_eq!(memory.read16(TIMER_BASE + index * 4).unwrap(), 0xffff);
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}
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assert_eq!(memory.read16(IF).unwrap(), 0);
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memory.advance_cycles(64);
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for index in 0..3 {
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assert_eq!(memory.read16(TIMER_BASE + index * 4).unwrap(), 0xfffe);
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}
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assert_eq!(memory.read16(TIMER_BASE + 12).unwrap(), 0xffff);
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assert_eq!(memory.read16(IF).unwrap(), 0x78);
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}
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#[test]
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fn leaving_cascade_joins_the_existing_divider_instead_of_starting_a_new_period() {
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let mut memory = Memory::new(Vec::new()).unwrap();
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start(&mut memory, 1, 0, 0x85); // Timer0 disabled: no cascade pulses.
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memory.advance_cycles(63);
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memory.write16(TIMER_BASE + 6, 0x81).unwrap();
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memory.advance_cycles(1);
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assert_eq!(memory.read16(TIMER_BASE + 4).unwrap(), 1);
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memory.write16(TIMER_BASE + 6, 0x85).unwrap();
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memory.advance_cycles(63);
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memory.write16(TIMER_BASE + 6, 0x81).unwrap();
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memory.advance_cycles(1);
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assert_eq!(memory.read16(TIMER_BASE + 4).unwrap(), 2);
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}
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#[test]
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fn halt_stops_at_the_shared_edge_and_stop_freezes_the_divider_until_keypad_wake() {
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let mut memory = Memory::new(Vec::new()).unwrap();
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memory.advance_cycles(63);
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start(&mut memory, 0, 0xffff, 0xc1);
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memory.write16(IE, 8).unwrap();
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memory.write8(HALTCNT, 0).unwrap();
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let mut machine = Machine::new(Cpu::new(ROM_START), memory);
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assert_eq!(machine.step().unwrap(), StepKind::HaltIdle);
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assert_eq!(machine.last_timing().idle_cycles, 1);
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assert_eq!(machine.cycles(), 64);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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assert!(!machine.halted());
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let mut memory = Memory::new(Vec::new()).unwrap();
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memory.advance_cycles(63);
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start(&mut memory, 0, 0, 0x81);
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memory.write16(IE, 0x1000).unwrap();
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memory.write16(KEYCNT, 0x4001).unwrap();
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memory.write8(HALTCNT, 0x80).unwrap();
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memory.advance_cycles(1000);
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assert_eq!(memory.cycles(), 63);
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memory.set_buttons(Buttons::from_bits(1));
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assert!(!memory.stopped());
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memory.advance_cycles(1);
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assert_eq!(memory.cycles(), 64);
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 1);
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}
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#[test]
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fn maximum_batches_keep_low_divider_bits_without_per_cycle_iteration() {
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let mut memory = Memory::new(Vec::new()).unwrap();
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memory.advance_cycles(u32::MAX); // Low ten bits are all set, even with no enabled timer.
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start(&mut memory, 0, 0, 0x83);
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memory.advance_cycles(1);
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 1);
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memory.advance_cycles(u32::MAX); // 4,194,303 ticks, wrapping the 16-bit counter to zero.
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 0);
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memory.advance_cycles(1);
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 1);
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assert_eq!(memory.cycles(), 2 * (u64::from(u32::MAX) + 1));
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}
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#[derive(Clone, Copy, Default)]
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struct ReferenceTimer {
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counter: u16,
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reload: u16,
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control: u16,
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}
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struct Reference {
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timers: [ReferenceTimer; 4],
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clock: u64,
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pending: u16,
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}
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impl Reference {
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fn control(&mut self, index: usize, value: u16) {
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let timer = &mut self.timers[index];
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let value = value & if index == 0 { 0xc3 } else { 0xc7 };
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if timer.control & 0x80 == 0 && value & 0x80 != 0 {
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timer.counter = timer.reload;
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}
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timer.control = value;
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}
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fn advance(&mut self, cycles: u32) {
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// Independent literal clock-edge simulation. No phase accumulator or bulk division.
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for _ in 0..cycles {
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self.clock += 1;
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let mut overflow = false;
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for (index, timer) in self.timers.iter_mut().enumerate() {
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let tick = timer.control & 0x80 != 0
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&& if timer.control & 4 != 0 {
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overflow
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} else {
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self.clock
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.is_multiple_of(DIVISORS[usize::from(timer.control & 3)])
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};
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overflow = tick && timer.counter == 0xffff;
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if overflow {
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timer.counter = timer.reload;
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if timer.control & 0x40 != 0 {
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self.pending |= 1 << (index + 3);
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}
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} else if tick {
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timer.counter += 1;
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}
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}
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}
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}
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}
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#[test]
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fn dynamic_control_reload_and_clock_sequences_match_independent_edge_simulation() {
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for mut seed in [0x1020_3040_u32, 0xdead_beef, 0x7654_3210] {
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let mut memory = Memory::new(Vec::new()).unwrap();
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let mut reference = Reference {
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timers: [ReferenceTimer::default(); 4],
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clock: 0,
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pending: 0,
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};
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for _ in 0..2000 {
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seed = seed.wrapping_mul(1664525).wrapping_add(1013904223);
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let index = ((seed >> 8) & 3) as usize;
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let address = TIMER_BASE + index as u32 * 4;
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match seed >> 29 {
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0 | 1 => {
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let value = ((seed >> 16) as u16 & 0xc7) | 0x80;
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memory.write16(address + 2, value).unwrap();
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reference.control(index, value);
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}
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2 => {
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memory.write16(address + 2, 0).unwrap();
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reference.control(index, 0);
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}
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3 => {
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let reload = 0xfff0 | ((seed >> 16) as u16 & 15);
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memory.write16(address, reload).unwrap();
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reference.timers[index].reload = reload;
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}
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4 => {
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let mask = (seed >> 16) as u16 & 0x78;
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memory.write16(IF, mask).unwrap();
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reference.pending &= !mask;
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}
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_ => {
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let cycles = (seed >> 16) & 2047;
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memory.advance_cycles(cycles);
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reference.advance(cycles);
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}
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}
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for (index, timer) in reference.timers.iter().enumerate() {
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assert_eq!(
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memory.read32(TIMER_BASE + index as u32 * 4).unwrap(),
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u32::from(timer.counter) | u32::from(timer.control) << 16
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);
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}
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assert_eq!(memory.read16(IF).unwrap(), reference.pending);
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assert_eq!(memory.cycles(), reference.clock);
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}
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}
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}
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@ -100,7 +100,7 @@ fn all_prescalers_retain_fractional_cycles_between_advances() {
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}
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#[test]
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fn clock_source_changes_and_restart_reset_provisional_phase() {
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fn clock_source_changes_and_restart_keep_the_shared_phase() {
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let mut bus = memory();
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bus.write32(TIMER_BASE, 0x0081_0000).unwrap(); // /64
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bus.advance_cycles(63);
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@ -108,16 +108,17 @@ fn clock_source_changes_and_restart_reset_provisional_phase() {
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bus.advance_cycles(1);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 1);
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bus.advance_cycles(63);
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bus.write16(TIMER_BASE + 2, 0x82).unwrap(); // /256 resets phase
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bus.advance_cycles(255);
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bus.write16(TIMER_BASE + 2, 0x82).unwrap(); // t=127: next shared /256 edge is t=256.
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bus.advance_cycles(128);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 1);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 2);
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bus.write16(TIMER_BASE + 2, 0).unwrap();
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bus.advance_cycles(255);
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bus.advance_cycles(255); // t=511; disabled time still advances the divider.
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bus.write16(TIMER_BASE + 2, 0x82).unwrap();
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bus.advance_cycles(255);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(TIMER_BASE).unwrap(), 1);
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}
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#[test]
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