fix(memory): ignore CPU and DMA writes to the Game Pak ROM windows
Stores to 0x08-0x0c returned ReadOnly and stopped the machine. Hardware ignores them, and a second game's boot code stores to a ROM mirror. Emulated writes now pay their bus cost and change nothing. The 0x0d window stays a diagnostic until EEPROM is modeled there, and host writes stay strict. Tests that used a ROM store as their failing write now cross an ignored ROM word into the 0x0d window. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HhfHfHEuzv2AUTd6erW1gU
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parent
66817c919d
commit
258fbff2fa
25 changed files with 86 additions and 74 deletions
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@ -437,8 +437,8 @@ fn protected_or_wrapping_source_ranges_return_without_copying() {
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}
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#[test]
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fn copy_failure_keeps_earlier_writes_but_not_partial_instruction_changes() {
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let (mut machine, _) = call(0x0b, false, [SOURCE, 0x07ff_fffc, 2 | (1 << 26)]);
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fn copy_failure_follows_an_ignored_rom_word_without_partial_instruction_changes() {
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let (mut machine, _) = call(0x0b, false, [SOURCE, 0x0cff_fffc, 2 | (1 << 26)]);
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machine.memory_mut().write32(SOURCE, 0xaabb_ccdd).unwrap();
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let mut failed = false;
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for _ in 0..100 {
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@ -448,12 +448,11 @@ fn copy_failure_keeps_earlier_writes_but_not_partial_instruction_changes() {
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if let Err(error) = machine.step() {
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assert_eq!(
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error,
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MachineError::Cpu(MemoryError::ReadOnly(0x0800_0000).into())
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.last_timing(), timing);
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assert_eq!(machine.memory().read32(0x07ff_fffc).unwrap(), 0xaabb_ccdd);
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failed = true;
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break;
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}
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@ -498,12 +498,11 @@ fn destination_failure_keeps_preceding_halfword_stores() {
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angle: 0,
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}])
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};
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let (mut m, _) = prepare(service, false, [DATA, 0x07ff_fffc, 1, 2], 0x1f, &data);
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let (mut m, _) = prepare(service, false, [DATA, 0x0cff_fffc, 1, 2], 0x1f, &data);
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assert_eq!(
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fail(&mut m),
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MachineError::Cpu(MemoryError::ReadOnly(ROM_START).into())
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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assert_eq!(m.memory().read32(0x07ff_fffc).unwrap(), 256);
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}
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}
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@ -361,10 +361,10 @@ fn truncated_descriptors_and_sources_return_memory_diagnostics() {
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}
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#[test]
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fn destination_failure_preserves_completed_word() {
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fn destination_failure_follows_an_ignored_rom_word() {
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let (mut m, _) = prepare(
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false,
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0x07ff_fffc,
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0x0cff_fffc,
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&[0x12, 0x34, 0x56, 0x78, 1, 2, 3, 4],
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8,
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8,
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@ -372,9 +372,8 @@ fn destination_failure_preserves_completed_word() {
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);
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assert_eq!(
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fail(&mut m),
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MachineError::Cpu(MemoryError::ReadOnly(ROM_START).into())
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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assert_eq!(m.memory().read32(0x07ff_fffc).unwrap(), 0x7856_3412);
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}
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#[test]
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@ -321,17 +321,13 @@ fn failed_source_reads_keep_completed_units_but_not_pending_halfwords() {
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}
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#[test]
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fn destination_failure_preserves_preceding_completed_halfword() {
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fn destination_failure_follows_an_ignored_rom_halfword() {
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for service in [0x17, 0x18] {
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let (data, _) = filtered(service, &[0x12, 0x34, 0x56, 0x78]);
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let (mut m, _) = prepare(service, false, 0x07ff_fffe, &data);
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let (mut m, _) = prepare(service, false, 0x0cff_fffe, &data);
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assert_eq!(
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fail(&mut m),
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MachineError::Cpu(MemoryError::ReadOnly(ROM_START).into())
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);
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assert_eq!(
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m.memory().read16(0x07ff_fffe).unwrap(),
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if service == 0x17 { 0x3412 } else { 0x12 }
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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}
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}
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@ -412,14 +412,13 @@ fn input_word_refill_failure_does_not_commit_incomplete_output() {
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}
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#[test]
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fn destination_failure_preserves_preceding_completed_word() {
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fn destination_failure_follows_an_ignored_rom_word() {
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let (data, _) = encode(8, &pair(), &[0x12; 8]);
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let (mut m, _) = prepare(false, 0x07ff_fffc, &data);
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let (mut m, _) = prepare(false, 0x0cff_fffc, &data);
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assert_eq!(
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fail(&mut m),
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MachineError::Cpu(MemoryError::ReadOnly(ROM_START).into())
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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assert_eq!(m.memory().read32(0x07ff_fffc).unwrap(), 0x1212_1212);
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}
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#[test]
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@ -431,10 +431,9 @@ fn destination_failure_preserves_preceding_completed_halfword() {
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Token::Literal(0x56),
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Token::Literal(0x78),
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]);
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let (mut machine, _) = prepare(0x12, false, 0x07ff_fffe, &compressed);
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let (mut machine, _) = prepare(0x12, false, 0x0cff_fffe, &compressed);
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assert_eq!(
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fail(&mut machine),
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MachineError::Cpu(MemoryError::ReadOnly(0x0800_0000).into())
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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assert_eq!(machine.memory().read16(0x07ff_fffe).unwrap(), 0x3412);
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}
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@ -317,14 +317,13 @@ fn incomplete_halfwords_are_not_committed_after_source_failure() {
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}
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#[test]
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fn destination_failure_preserves_earlier_completed_writes() {
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fn destination_failure_follows_an_ignored_rom_halfword() {
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let (data, _) = stream(&[Block::Literal(vec![0x12, 0x34, 0x56, 0x78])]);
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let (mut m, _) = prepare(0x15, false, 0x07ff_fffe, &data);
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let (mut m, _) = prepare(0x15, false, 0x0cff_fffe, &data);
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assert_eq!(
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fail(&mut m),
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MachineError::Cpu(MemoryError::ReadOnly(ROM_START).into())
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MachineError::Cpu(MemoryError::ReadOnly(0x0d00_0000).into())
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);
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assert_eq!(m.memory().read16(0x07ff_fffe).unwrap(), 0x3412);
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}
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#[test]
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@ -686,10 +686,10 @@ fn invalid_memory_and_dma_register_destinations_are_diagnostics() {
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),
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(
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SOURCE,
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ROM_START,
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0x0d00_0000,
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DmaError::Memory {
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channel: 3,
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error: MemoryError::ReadOnly(ROM_START),
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error: MemoryError::ReadOnly(0x0d00_0000),
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},
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),
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(
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@ -145,12 +145,12 @@ fn zero_is_known_data_not_an_unknown_latch() {
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fn failed_units_preserve_the_old_latch_without_new_data_or_irq() {
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for (source, destination, control) in [
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(0x0e00_0000, DEST, 0x4400), // Unmapped reads do not use a known latch.
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(SOURCE, ROM_START, 0x4400),
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(SOURCE, 0x0d00_0000, 0x4400),
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(SOURCE, 0x0400_0058, 0x4400),
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(SOURCE, DMA_BASE, 0x4400),
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(SOURCE, 0x0400_0300, 0x4400),
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(SOURCE, DEST, 0x4580), // Unsupported source mode.
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(0, ROM_START, 0x4400), // A blocked source cannot bypass destination checks.
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(SOURCE, DEST, 0x4580), // Unsupported source mode.
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(0, 0x0d00_0000, 0x4400), // A blocked source cannot bypass destination checks.
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] {
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let mut machine = machine();
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seed(&mut machine, 3, DATA);
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@ -175,7 +175,7 @@ fn failed_units_preserve_the_old_latch_without_new_data_or_irq() {
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fn failed_destination_does_not_seed_a_cold_channel() {
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let mut machine = machine();
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machine.memory_mut().write32(SOURCE, DATA).unwrap();
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configure(machine.memory_mut(), 3, SOURCE, ROM_START, 1, 0x400);
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configure(machine.memory_mut(), 3, SOURCE, 0x0d00_0000, 1, 0x400);
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assert!(machine.step().is_err());
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machine.memory_mut().write16(base(3) + 10, 0).unwrap();
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configure(machine.memory_mut(), 3, 0, DEST, 1, 0x400);
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