fix(memory): ignore CPU and DMA writes to unused I/O addresses
Stores to I/O addresses with no register returned Unmapped and stopped the machine. Hardware ignores them. Emulated writes there now pay their bus cost and change nothing; host writes stay strict. The unmodeled internal memory control register at 0x04xx0800 and all unused I/O reads remain diagnostics. Rollback tests that used unused I/O as their failing word now run the block on to a register that rejects the stored value: SIOMULTI2 outside multiplayer mode, an RCNT GPIO serial IRQ, or 64-sample wave playback. Where no reachable register can fail (JOYSTAT, POSTFLG/HALTCNT, IME, DMA3CNT), the test now checks that the block commits and the unused word is ignored. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HhfHfHEuzv2AUTd6erW1gU
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parent
b535c08313
commit
20176716d9
16 changed files with 166 additions and 92 deletions
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@ -371,8 +371,23 @@ fn cpu_store_samples_keys_then_irq_enters_on_the_following_step() {
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#[test]
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fn failed_block_store_does_not_commit_key_control_irq_history_or_halt_wake() {
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// STMIA r0!,{r1,r2}: keypad word is valid, but RCNT's upper padding is not mapped.
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let mut m = prepared(0xe8a0_0006, KEYINPUT, 0x4001_0000);
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// STMIA r0!,{r1,r2}: the keypad word is valid, but RCNT enables a GPIO serial IRQ.
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let mut mem = Memory::new(words(&[
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0xe59f_000c,
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0xe59f_100c,
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0xe59f_200c,
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0xe8a0_0006,
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0xeaff_fffe,
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KEYINPUT,
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0x4001_0000,
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0x0000_8100,
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]))
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.unwrap();
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let mut cpu = Cpu::new(ROM_START);
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for _ in 0..3 {
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cpu.step(&mut mem).unwrap();
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}
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let mut m = Machine::new(cpu, mem);
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press(m.memory_mut(), 1);
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m.memory_mut().write16(IE, IRQ).unwrap();
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let before = m.cpu().clone();
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@ -380,9 +395,13 @@ fn failed_block_store_does_not_commit_key_control_irq_history_or_halt_wake() {
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let timing = m.last_timing();
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assert_eq!(
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m.step(),
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Err(MachineError::Cpu(CpuError::Memory(MemoryError::Unmapped(
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KEYINPUT + 6
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))))
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Err(MachineError::Cpu(CpuError::Memory(
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MemoryError::UnsupportedIo {
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address: KEYINPUT + 5,
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value: 0x81,
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operation: "GPIO serial interrupt enable",
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}
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)))
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);
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assert_eq!(m.cpu(), &before);
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assert_eq!(m.cycles(), cycles);
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