fix(memory): ignore CPU and DMA writes to unused I/O addresses
Stores to I/O addresses with no register returned Unmapped and stopped the machine. Hardware ignores them. Emulated writes there now pay their bus cost and change nothing; host writes stay strict. The unmodeled internal memory control register at 0x04xx0800 and all unused I/O reads remain diagnostics. Rollback tests that used unused I/O as their failing word now run the block on to a register that rejects the stored value: SIOMULTI2 outside multiplayer mode, an RCNT GPIO serial IRQ, or 64-sample wave playback. Where no reachable register can fail (JOYSTAT, POSTFLG/HALTCNT, IME, DMA3CNT), the test now checks that the block commits and the unused word is ignored. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HhfHfHEuzv2AUTd6erW1gU
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parent
b535c08313
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20176716d9
16 changed files with 166 additions and 92 deletions
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@ -749,13 +749,14 @@ fn failing_later_unit_preserves_earlier_data_but_not_partial_current_unit() {
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}
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#[test]
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fn failed_io_write_does_not_partially_change_display_control() {
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fn unused_io_destination_is_ignored_without_changing_display_control() {
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let mut machine = machine();
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machine.memory_mut().write32(SOURCE, 0xffff_ffff).unwrap();
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configure(machine.memory_mut(), 3, SOURCE, 0x0400_0058, 1, 0x400);
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assert!(machine.step().is_err());
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units(&mut machine, 3, 1);
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assert!(!enabled(&machine, 3));
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assert_eq!(machine.memory().read16(DISPCNT).unwrap(), 0);
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assert_eq!(machine.cycles(), 0);
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assert!(machine.cycles() > 0);
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}
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#[test]
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@ -787,11 +788,11 @@ fn cpu_can_enable_dma_with_a_combined_count_control_store() {
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}
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#[test]
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fn failed_cpu_block_store_cannot_enable_dma_or_change_its_hidden_latches() {
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fn cpu_block_store_past_dma3_control_enables_the_channel_and_ignores_unused_io() {
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let rom = words(&[
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0xe59f_000c, // LDR r0,[pc,#12] (DMA3CNT)
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0xe59f_100c, // LDR r1,[pc,#12] (count/control)
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0xe8a0_0006, // STMIA r0!,{r1,r2}; second word unmapped.
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0xe8a0_0006, // STMIA r0!,{r1,r2}; the second word is unused I/O.
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0xeaff_fffe,
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0xe1a0_0000,
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base(3) + 8,
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@ -803,15 +804,14 @@ fn failed_cpu_block_store_cannot_enable_dma_or_change_its_hidden_latches() {
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cpu.step(&mut bus).unwrap();
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configure(&mut bus, 3, SOURCE, DEST, 2, 0);
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bus.write16(base(3) + 10, 0).unwrap();
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let before = cpu.clone();
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bus.write32(SOURCE, 0x1234_5678).unwrap();
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let mut machine = Machine::new(cpu, bus);
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assert!(matches!(machine.step(), Err(MachineError::Cpu(_))));
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assert_eq!(machine.cpu(), &before);
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assert!(!enabled(&machine, 3));
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assert_eq!(machine.cycles(), 0);
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machine.memory_mut().write16(base(3) + 10, 0x8000).unwrap();
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units(&mut machine, 3, 2); // The count latch is still 2, not 1.
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[0], base(3) + 16);
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assert!(enabled(&machine, 3));
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units(&mut machine, 3, 1); // The store latched a count of 1.
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assert!(!enabled(&machine, 3));
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assert_eq!(machine.memory().read32(DEST).unwrap(), 0x1234_5678);
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}
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#[test]
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