feat(timing): break CPU sequential access after DMA

Retain one pending non-sequential resume after successful DMA. Apply it to the next nominal non-refill code access and consume it only on successful CPU or IRQ progress. Preserve failed-step atomicity, host and idle isolation, existing refill costs, and WAITCNT ordering.

Add 13 original regressions for ARM/Thumb widths, ROM wait settings, sources, preemption, retries, mixed APIs, idle states, and interrupt timing. Record pinned hardware-test source and emulator evidence without claiming physical-hardware or full-pipeline conformance.

Validated on Darwin arm64: 952 workspace and 883 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain unchanged.

crates/gba-core/src/cpu.rs

@@ -18,6 +18,8 @@ mod bios_access_tests;
 #[cfg(test)]
 mod compare_psr_tests;
 #[cfg(test)]
+mod dma_resume_tests;
+#[cfg(test)]
 mod exception_tests;
 #[cfg(test)]
 mod instruction_tests;