feat(timing): break CPU sequential access after DMA
Retain one pending non-sequential resume after successful DMA. Apply it to the next nominal non-refill code access and consume it only on successful CPU or IRQ progress. Preserve failed-step atomicity, host and idle isolation, existing refill costs, and WAITCNT ordering. Add 13 original regressions for ARM/Thumb widths, ROM wait settings, sources, preemption, retries, mixed APIs, idle states, and interrupt timing. Record pinned hardware-test source and emulator evidence without claiming physical-hardware or full-pipeline conformance. Validated on Darwin arm64: 952 workspace and 883 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain unchanged.
This commit is contained in:
0xrsydn
parent
663b25e5d1
commit
16286e0cbd
11 changed files with 437 additions and 4 deletions
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@ -18,6 +18,8 @@ mod bios_access_tests;
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#[cfg(test)]
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mod compare_psr_tests;
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#[cfg(test)]
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mod dma_resume_tests;
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#[cfg(test)]
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mod exception_tests;
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#[cfg(test)]
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mod instruction_tests;
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302
crates/gba-core/src/cpu/dma_resume_tests.rs
Normal file
302
crates/gba-core/src/cpu/dma_resume_tests.rs
Normal file
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@ -0,0 +1,302 @@
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//! Original tests of the nominal, instruction-boundary DMA resume cost.
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use super::*;
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use crate::{
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dma::{DMA_BASE, DMA_STRIDE},
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input::Buttons,
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io::{HALTCNT, IE, IME, KEYCNT, TIMER_BASE, WAITCNT},
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machine::{Machine, StepKind},
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memory::{BIOS_SIZE, ROM_START},
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};
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const RAM: u32 = 0x0200_1000;
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const DEST: u32 = 0x0300_1000;
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const PC: u32 = ROM_START + 0x100;
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fn program(thumb: bool, pc: u32, instruction: u32) -> (Cpu, Memory) {
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let nop = if thumb { 0x46c0_46c0_u32 } else { 0xe1a0_0000 };
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let offset = (pc & 0x01ff_ffff) as usize;
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let mut rom = nop.to_le_bytes().repeat((offset + 32) / 4);
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let width = if thumb { 2 } else { 4 };
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rom[offset..offset + width].copy_from_slice(&instruction.to_le_bytes()[..width]);
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let mut cpu = Cpu::new(pc);
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if thumb {
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cpu.instruction_set = InstructionSet::Thumb;
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}
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cpu.registers[1] = RAM;
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(cpu, Memory::new(rom).unwrap())
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}
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fn configure(bus: &mut Memory, channel: usize, source: u32, destination: u32, count: u16) {
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let base = DMA_BASE + channel as u32 * DMA_STRIDE;
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bus.write16(base + 10, 0).unwrap();
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bus.write32(base, source).unwrap();
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bus.write32(base + 4, destination).unwrap();
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bus.write32(base + 8, 0x8400_0000 | u32::from(count))
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.unwrap();
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}
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fn dma(bus: &mut Memory) {
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configure(bus, 3, RAM, DEST, 1);
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assert_eq!(bus.step_dma().unwrap().unwrap().0, 3);
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}
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#[test]
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fn first_post_dma_code_access_uses_n_then_s_for_all_rom_wait_settings() {
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for thumb in [false, true] {
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for window in 0..3 {
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for first in 0..4 {
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for second in 0..2 {
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for prefetch in [0, 0x4000] {
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let pc = PC + window as u32 * 0x0200_0000;
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let instruction = if thumb { 0x46c0 } else { 0xe1a0_0000 };
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let (mut cpu, mut bus) = program(thumb, pc, instruction);
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let waitcnt = (first << [2, 5, 8][window])
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| (second << [4, 7, 10][window])
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| prefetch;
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bus.write16(WAITCNT, waitcnt).unwrap();
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dma(&mut bus);
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// Independent table, not the production timing helper.
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let n = [5, 4, 3, 9][first as usize];
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let s = if second == 1 { 2 } else { [3, 5, 9][window] };
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assert_eq!(
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cpu.step_timed(&mut bus).unwrap().code_cycles,
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n + if thumb { 0 } else { s }
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);
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assert_eq!(
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cpu.step_timed(&mut bus).unwrap().code_cycles,
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if thumb { s } else { 2 * s }
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);
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assert_eq!(bus.cycles(), 9); // CPU-only timed calls do not advance devices.
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}
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}
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}
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}
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}
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}
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#[test]
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fn ram_and_rom_dma_sources_both_break_the_cpu_sequence() {
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for source in [RAM, DEST, ROM_START] {
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let (cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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configure(&mut bus, 3, source, DEST + 16, 1);
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let mut machine = Machine::new(cpu, bus);
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.last_timing().code_cycles, 8);
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 6);
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}
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}
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#[test]
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fn register_configuration_alone_is_not_a_dma_resume_but_blocked_source_completion_is() {
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let (mut cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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configure(&mut bus, 3, RAM, DEST, 1);
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// CPU-only execution does not service the configured transfer.
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 6);
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bus.step_dma().unwrap().unwrap();
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 8);
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configure(&mut bus, 3, 0, DEST, 1); // Known channel data, no BIOS read.
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bus.step_dma().unwrap().unwrap();
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 8);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 6);
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}
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#[test]
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fn multiple_units_and_channel_preemption_produce_one_resume_not_a_penalty_queue() {
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let (cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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configure(&mut bus, 3, RAM, DEST, 2);
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let mut machine = Machine::new(cpu, bus);
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machine.step().unwrap();
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configure(machine.memory_mut(), 0, RAM + 16, DEST + 16, 1);
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for channel in [0, 3] {
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel });
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}
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 8);
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 6);
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// Another block after CPU progress must mark the next resume again.
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configure(machine.memory_mut(), 3, RAM, DEST, 1);
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machine.step().unwrap();
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 8);
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}
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#[test]
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fn failed_dma_preserves_an_existing_resume_but_cannot_create_one() {
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for completed in [false, true] {
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let (mut cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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if completed {
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dma(&mut bus);
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}
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configure(&mut bus, 3, 0x0e00_0000, DEST, 1);
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let cycles = bus.cycles();
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for _ in 0..2 {
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assert!(bus.step_dma().is_err());
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assert_eq!(bus.cycles(), cycles);
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}
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bus.write16(DMA_BASE + 3 * DMA_STRIDE + 10, 0).unwrap();
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assert_eq!(
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cpu.step_timed(&mut bus).unwrap().code_cycles,
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if completed { 8 } else { 6 }
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);
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}
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}
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#[test]
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fn failed_cpu_fetch_and_data_access_preserve_resume_until_success() {
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let (mut cpu, mut bus) = program(false, PC, 0xe591_0000); // LDR r0,[r1].
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dma(&mut bus);
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cpu.registers[15] = 0x0e00_0000;
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assert!(cpu.step_timed(&mut bus).is_err());
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bus.write32(DEST + 0x100, 0xffff_ffff).unwrap(); // Unsupported ARM encoding.
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cpu.registers[15] = DEST + 0x100;
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assert!(cpu.step_timed(&mut bus).is_err());
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cpu.registers[15] = PC;
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cpu.registers[1] = 0x0e00_0000;
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let before = cpu.clone();
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for _ in 0..2 {
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assert!(cpu.step_timed(&mut bus).is_err());
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assert_eq!(cpu, before);
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}
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cpu.registers[1] = RAM;
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(timing.code_cycles, 8);
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assert_eq!(timing.data_cycles, 6);
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assert_eq!(timing.internal_cycles, 1);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 6);
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}
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#[test]
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fn host_accesses_and_clock_advances_do_not_consume_resume_but_untimed_cpu_does() {
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for untimed in [false, true] {
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let (mut cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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dma(&mut bus);
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bus.read32(PC).unwrap();
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bus.read32(RAM).unwrap();
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bus.write32(DEST, 0).unwrap();
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bus.advance_cycles(10);
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if untimed {
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cpu.step(&mut bus).unwrap();
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}
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assert_eq!(
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cpu.step_timed(&mut bus).unwrap().code_cycles,
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if untimed { 6 } else { 8 }
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);
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}
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}
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#[test]
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fn skipped_conditions_stores_and_boundaries_consume_resume_without_double_charging() {
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for (pc, instruction, data) in [
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(PC, 0x0591_0000, 0), // LDREQ skipped: Z is clear.
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(PC, 0xe581_0000, 6), // STR already has an N code access.
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(ROM_START + 0x20000, 0xe1a0_0000, 0), // Boundary already forces N.
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] {
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let (mut cpu, mut bus) = program(false, pc, instruction);
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dma(&mut bus);
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(timing.code_cycles, 8);
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assert_eq!(timing.data_cycles, data);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 6);
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}
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}
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#[test]
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fn waitcnt_cpu_store_uses_old_code_cost_but_dma_store_applies_before_resume() {
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let (mut cpu, mut bus) = program(false, PC, 0xe581_0000);
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cpu.registers[0] = 0x18;
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cpu.registers[1] = WAITCNT;
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dma(&mut bus);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 8);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 4);
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let (mut cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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bus.write32(RAM, 0x18).unwrap();
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configure(&mut bus, 3, RAM, WAITCNT, 1);
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bus.step_dma().unwrap().unwrap();
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 5); // N=3, S=2.
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 4);
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}
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#[test]
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fn ram_instruction_consumes_resume_instead_of_delaying_it_until_rom_execution() {
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let (mut cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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bus.write32(DEST + 0x100, 0xe1a0_0000).unwrap();
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cpu.registers[15] = DEST + 0x100;
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dma(&mut bus);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 1);
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cpu.registers[15] = PC;
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 6);
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}
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#[test]
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fn branch_refill_and_irq_entry_consume_resume_without_an_extra_nominal_access() {
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let (mut cpu, mut bus) = program(false, PC, 0xea00_0000); // B PC+8.
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dma(&mut bus);
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 20); // Existing N+2S summary.
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assert_eq!(cpu.step_timed(&mut bus).unwrap().code_cycles, 6);
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let (cpu, _) = program(false, PC, 0xe1a0_0000);
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let mut bios = vec![0; BIOS_SIZE];
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bios[0x18..0x1c].copy_from_slice(&0xe1a0_0000_u32.to_le_bytes());
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let mut bus = Memory::with_bios(0xe1a0_0000_u32.to_le_bytes().repeat(80), bios).unwrap();
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configure(&mut bus, 3, RAM, DEST, 1);
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bus.write16(DMA_BASE + 3 * DMA_STRIDE + 10, 0xc400).unwrap();
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bus.write16(IE, 1 << 11).unwrap();
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bus.write16(IME, 1).unwrap();
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let mut machine = Machine::new(cpu, bus);
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.last_timing().code_cycles, 3);
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// Inspect the bus through a separate CPU after IRQ entry, before a handler runs.
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let mut probe = Cpu::new(PC);
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assert_eq!(
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probe.step_timed(machine.memory_mut()).unwrap().code_cycles,
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6
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);
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assert_eq!(machine.memory().cycles(), 12);
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}
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#[test]
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fn halt_and_stop_idle_do_not_consume_a_completed_dma_resume() {
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for stop in [false, true] {
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let (cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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dma(&mut bus);
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let mut machine = Machine::new(cpu, bus);
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if stop {
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machine.memory_mut().write16(KEYCNT, 0x4001).unwrap();
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machine.memory_mut().write16(IE, 1 << 12).unwrap();
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machine.memory_mut().write8(HALTCNT, 0x80).unwrap();
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assert_eq!(machine.step().unwrap(), StepKind::StopIdle);
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machine.memory_mut().set_buttons(Buttons::from_bits(1));
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} else {
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machine.memory_mut().write16(IE, 8).unwrap();
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machine
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.memory_mut()
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.write32(TIMER_BASE, 0x00c0_fff0)
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.unwrap();
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machine.memory_mut().write8(HALTCNT, 0).unwrap();
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assert_eq!(machine.step().unwrap(), StepKind::HaltIdle);
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}
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.last_timing().code_cycles, 8);
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 6);
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}
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}
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#[test]
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fn resumed_n_cost_advances_devices_and_defers_irq_to_the_following_step() {
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let (cpu, mut bus) = program(false, PC, 0xe1a0_0000);
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dma(&mut bus);
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bus.write32(TIMER_BASE, 0x00c0_fff9).unwrap(); // Overflow after seven cycles.
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bus.write16(IE, 8).unwrap();
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bus.write16(IME, 1).unwrap();
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let mut machine = Machine::new(cpu, bus);
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let start = machine.cycles();
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cycles() - start, 8);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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}
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@ -59,6 +59,7 @@ impl Cpu {
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let width = self.instruction_set.access_width();
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// A WAITCNT store affects subsequent instructions, not this code access.
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let waitcnt = memory.waitcnt();
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let code_kind = memory.cpu_code_kind(summary.code_kind);
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memory.begin_data_timing();
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let result = self.execute_fetched(instruction, memory);
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let data_cycles = memory.end_data_timing();
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@ -66,7 +67,7 @@ impl Cpu {
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let code_cycles = if summary.refill {
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refill_cycles(waitcnt, self.pc(), self.instruction_set.access_width())
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} else {
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bus_cycles(waitcnt, pc, width, summary.code_kind)
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bus_cycles(waitcnt, pc, width, code_kind)
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};
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Ok(StepTiming {
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code_cycles,
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@ -81,6 +81,8 @@ pub struct Memory {
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io: Io,
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cycles: u64,
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data_timing: Cell<Option<DataTiming>>,
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// A completed DMA unit breaks the CPU's next nominal code-access sequence.
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cpu_resume_nonsequential: bool,
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cpu_access: Option<CpuAccess>,
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bios_prefetch: Option<u32>,
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iwram_bus: IwramBus,
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@ -104,6 +106,7 @@ impl Memory {
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io: Io::default(),
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cycles: 0,
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data_timing: Cell::new(None),
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cpu_resume_nonsequential: false,
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cpu_access: None,
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bios_prefetch: None,
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iwram_bus: IwramBus::default(),
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@ -141,6 +144,8 @@ impl Memory {
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/// Finish the instruction/IRQ entry that started while running. A STOP store
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/// still pays its full nominal cost before later steps freeze the system.
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pub(crate) fn complete_cpu_step(&mut self, cycles: u32) {
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// IRQ entry consumes the resume too, without executing an instruction.
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self.cpu_resume_nonsequential = false;
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self.advance_running_cycles(cycles);
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}
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@ -341,6 +346,7 @@ impl Memory {
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// queue a second block while the current block is still transferring.
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self.advance_cycles(timing.total());
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self.io.complete_dma_unit(channel, data_latch);
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self.cpu_resume_nonsequential = true;
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Ok(Some((channel, timing)))
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}
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@ -413,6 +419,10 @@ impl Memory {
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}
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pub(crate) fn end_cpu_access(&mut self, succeeded: bool, sequential: bool) {
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if succeeded {
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// Timed and untimed CPU execution both consume a resume. Errors do not.
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self.cpu_resume_nonsequential = false;
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}
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self.iwram_bus.finish(succeeded, sequential);
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if let Some(access) = self.cpu_access.take() {
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if succeeded && access.pc < BIOS_SIZE as u32 {
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@ -486,6 +496,16 @@ impl Memory {
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self.io.waitcnt()
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}
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/// Resolve the next nominal code access without consuming pending DMA history.
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/// Successful instruction/IRQ completion consumes it; host reads and idle do not.
|
||||
pub(crate) fn cpu_code_kind(&self, kind: AccessKind) -> AccessKind {
|
||||
if self.cpu_resume_nonsequential {
|
||||
AccessKind::NonSequential
|
||||
} else {
|
||||
kind
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) fn begin_data_timing(&self) {
|
||||
debug_assert!(self.data_timing.get().is_none());
|
||||
self.data_timing.set(Some(DataTiming::default()));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue