feat(serial): clock disconnected normal transfers and completion IRQs
This commit is contained in:
0xrsydn
parent
d329c76dc3
commit
0b36ef1e24
17 changed files with 860 additions and 196 deletions
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@ -1,15 +1,16 @@
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//! GBA I/O subset: DMA, timers, interrupts, WAITCNT, display, keypad input,
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//! Direct Sound, and disconnected serial state with external-clock waiting.
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//! Direct Sound, and disconnected normal serial transfers.
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//! Timers share a free-running prescaler phase. Hardware startup/write delays
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//! and interrupt delivery delays are not modeled.
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mod inactive;
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mod serial;
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use crate::audio::Audio;
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pub use crate::audio::{FIFO_A, FIFO_B, SOUNDBIAS, SOUNDCNT_H, SOUNDCNT_X, SOUND_START, WAVE_RAM};
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pub use inactive::{JOYCNT, JOY_RECV, JOY_TRANS, RCNT, SIOCNT, SIODATA32, SIODATA8};
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pub(crate) use serial::Serial;
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pub use serial::{JOYCNT, JOY_RECV, JOY_TRANS, RCNT, SIOCNT, SIODATA32, SIODATA8};
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mod timer_step;
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pub(crate) use timer_step::TimerStep;
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use timer_step::TIMER_IRQ_MASK;
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use timer_step::STAGED_IRQ_MASK;
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use crate::{
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display::{Display, DisplayPosition, CYCLES_PER_LINE, HBLANK_START, VISIBLE_LINES},
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@ -155,7 +156,7 @@ enum PowerState {
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#[derive(Debug, Default, Clone, PartialEq, Eq)]
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pub(crate) struct Io {
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inactive: inactive::Inactive,
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pub(crate) serial: Serial,
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pub(crate) audio: Audio,
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timers: [Timer; 4],
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// Low ten system-clock bits cover every supported divider. STOP freezes this phase.
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@ -182,20 +183,20 @@ pub(crate) struct Io {
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impl Io {
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pub(crate) fn mapped(address: u32) -> bool {
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Audio::mapped(address)
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|| inactive::Inactive::mapped(address)
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|| Serial::mapped(address)
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|| matches!(address, 0x0400_0000..=0x0400_0057 | DMA_BASE..=DMA_END | 0x0400_0100..=0x0400_010f | 0x0400_0130..=0x0400_0133 | 0x0400_0200..=0x0400_020b | POSTFLG..=0x0400_0303)
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}
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pub(crate) fn unsupported_write(address: u32, value: u8) -> Option<&'static str> {
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inactive::Inactive::unsupported(address, value)
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Serial::unsupported(address, value)
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}
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pub(crate) fn read8(&self, address: u32) -> Option<u8> {
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if Audio::mapped(address) {
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return self.audio.read8(address);
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}
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if inactive::Inactive::mapped(address) {
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return self.inactive.read8(address);
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if Serial::mapped(address) {
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return self.serial.read8(address);
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}
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if (DMA_BASE..=DMA_END).contains(&address) {
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return Some(self.dma.read8(address));
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@ -235,8 +236,8 @@ impl Io {
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pub(crate) fn write8(&mut self, address: u32, value: u8) {
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debug_assert!(Self::mapped(address));
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debug_assert!(!(KEYINPUT..=KEYCNT + 1).contains(&address));
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if inactive::Inactive::mapped(address) {
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self.inactive.write8(address, value);
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if Serial::mapped(address) {
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self.serial.write(address, &[value]);
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return;
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}
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if (DMA_BASE..=DMA_END).contains(&address) {
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@ -336,12 +337,13 @@ impl Io {
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}
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}
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/// Bound an idle batch by the next display edge or independent timer overflow.
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/// Bound idle by the next display edge, timer overflow, or serial completion.
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/// Display edges keep this finite even without an enabled wake source.
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pub(crate) fn next_event_cycles(&self) -> u32 {
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self.timers
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.iter()
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.filter_map(|timer| timer.next_overflow(self.timer_phase))
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.chain(self.serial.next_event_cycles())
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.fold(self.display.next_event_cycles(), u32::min)
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}
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@ -425,10 +427,11 @@ impl Io {
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pub(crate) fn commit_timer_step(&mut self, step: TimerStep) {
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self.audio = step.audio;
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self.serial = step.serial;
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self.dma.trigger_sound(self.audio.take_requests());
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self.timers = step.timers;
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self.timer_phase = step.phase;
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self.pending = (self.pending & !TIMER_IRQ_MASK) | step.pending;
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self.pending = (self.pending & !STAGED_IRQ_MASK) | step.pending;
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self.wake_if_requested();
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}
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@ -486,6 +489,7 @@ impl Io {
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self.dma.trigger(vblank, hblank);
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self.pending |= self.display.advance(cycles);
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if advance_timers {
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self.pending |= self.serial.advance(cycles);
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self.pending |= Self::advance_timer_bank(
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&mut self.timers,
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&mut self.timer_phase,
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@ -1,94 +0,0 @@
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//! Disconnected serial state, including external-clock requests that cannot progress.
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use super::replace_byte;
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pub const SIODATA32: u32 = 0x0400_0120;
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pub const SIOCNT: u32 = 0x0400_0128;
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pub const SIODATA8: u32 = 0x0400_012a;
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pub const RCNT: u32 = 0x0400_0134;
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pub const JOYCNT: u32 = 0x0400_0140;
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pub const JOY_RECV: u32 = 0x0400_0150;
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pub const JOY_TRANS: u32 = 0x0400_0154;
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#[derive(Debug, Default, Clone, PartialEq, Eq)]
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pub(super) struct Inactive {
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serial_data: [u8; 4],
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serial_send: u8,
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serial_control: u16,
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rcnt: u16,
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}
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impl Inactive {
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pub(super) fn mapped(address: u32) -> bool {
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matches!(address,
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SIODATA32..=0x0400_0123 | SIOCNT..=0x0400_012b |
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RCNT..=0x0400_0135 | JOYCNT..=0x0400_0141 |
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JOY_RECV..=0x0400_0157)
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}
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/// Value-dependent rejection is independent of device state, so batch
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/// stores can validate all values before committing any RAM/I/O writes.
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/// RCNT mode and IRQ-enable bits share the high byte. Each high-byte write
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/// supplies the complete selection, independent of the previous low byte.
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pub(super) fn unsupported(address: u32, value: u8) -> Option<&'static str> {
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match address {
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// Clock source and start share the low byte. With no external
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// clock edges, an external-clock request only latches start/busy.
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SIOCNT if value & 0x81 == 0x81 => Some("internally clocked serial transfer"),
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0x0400_0129 if value & 0x20 != 0 => Some("multiplayer/UART serial mode"),
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0x0400_0135 if value & 0xc0 == 0xc0 => Some("Joybus serial mode"),
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0x0400_0135 if value & 0x81 == 0x81 => Some("GPIO serial interrupt enable"),
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JOYCNT if value & 0x40 != 0 => Some("Joybus interrupt enable"),
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JOY_RECV..=0x0400_0157 if value != 0 => Some("Joybus data access beyond reset"),
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_ => None,
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}
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}
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fn gpio_pins(&self) -> u16 {
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let outputs = (self.rcnt >> 4) & 15;
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(self.rcnt & outputs & 15) | (!outputs & 15) // Disconnected inputs have pull-ups.
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}
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pub(super) fn read8(&self, address: u32) -> Option<u8> {
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if (SIODATA32..=SIODATA32 + 3).contains(&address) {
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return Some(self.serial_data[(address - SIODATA32) as usize]);
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}
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let value = match address & !1 {
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SIOCNT => {
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let si = if self.rcnt & 0x8000 != 0 {
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self.gpio_pins() & 4
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} else {
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4
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};
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self.serial_control | si
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}
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SIODATA8 => u16::from(self.serial_send),
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RCNT => {
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// Normal-mode RCNT low pin samples are outside this subset.
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if self.rcnt & 0x8000 == 0 && address & 1 == 0 {
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return None;
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}
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(self.rcnt & !15) | self.gpio_pins()
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}
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JOYCNT | JOY_RECV..=0x0400_0156 => 0, // Only reset-state Joybus accesses are supported.
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_ => return None,
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};
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Some(value.to_le_bytes()[(address & 1) as usize])
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}
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pub(super) fn write8(&mut self, address: u32, value: u8) {
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debug_assert!(Self::unsupported(address, value).is_none());
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if (SIODATA32..=SIODATA32 + 3).contains(&address) {
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self.serial_data[(address - SIODATA32) as usize] = value;
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return;
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}
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match address & !1 {
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SIOCNT => {
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self.serial_control = replace_byte(self.serial_control, address, value) & 0x508b
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}
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SIODATA8 if address & 1 == 0 => self.serial_send = value,
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RCNT => self.rcnt = replace_byte(self.rcnt, address, value) & 0xc1ff,
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_ => {} // Unused/read-only bits have no effect.
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}
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}
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}
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195
crates/gba-core/src/io/serial.rs
Normal file
195
crates/gba-core/src/io/serial.rs
Normal file
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@ -0,0 +1,195 @@
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//! Disconnected normal serial shifter with nominal internal clocks.
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use super::replace_byte;
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pub const SIODATA32: u32 = 0x0400_0120;
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pub const SIOCNT: u32 = 0x0400_0128;
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pub const SIODATA8: u32 = 0x0400_012a;
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pub const RCNT: u32 = 0x0400_0134;
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pub const JOYCNT: u32 = 0x0400_0140;
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pub const JOY_RECV: u32 = 0x0400_0150;
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pub const JOY_TRANS: u32 = 0x0400_0154;
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub(crate) struct Serial {
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data: u32,
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send: u8,
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control: u16,
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rcnt: u16,
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bits_left: u8,
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until_bit: u32,
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}
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impl Serial {
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pub(crate) fn mapped(address: u32) -> bool {
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matches!(address,
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SIODATA32..=0x0400_0123 | SIOCNT..=0x0400_012b |
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RCNT..=0x0400_0135 | JOYCNT..=0x0400_0141 |
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JOY_RECV..=0x0400_0157)
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}
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pub(crate) fn unsupported(address: u32, value: u8) -> Option<&'static str> {
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match address {
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0x0400_0129 if value & 0x20 != 0 => Some("multiplayer/UART serial mode"),
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0x0400_0135 if value & 0xc0 == 0xc0 => Some("Joybus serial mode"),
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0x0400_0135 if value & 0x81 == 0x81 => Some("GPIO serial interrupt enable"),
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JOYCNT if value & 0x40 != 0 => Some("Joybus interrupt enable"),
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JOY_RECV..=0x0400_0157 if value != 0 => Some("Joybus data access beyond reset"),
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_ => None,
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}
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}
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fn normal(&self) -> bool {
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self.rcnt & 0x8000 == 0
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}
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fn busy(&self) -> bool {
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self.control & 0x80 != 0
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}
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fn clocked(&self) -> bool {
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self.normal() && self.busy() && self.control & 1 != 0
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}
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fn width(&self) -> u8 {
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if self.control & 0x1000 != 0 {
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32
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} else {
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8
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}
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}
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fn period(&self) -> u32 {
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if self.control & 2 != 0 {
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8
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} else {
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64
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}
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}
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/// Validate the final access value at its bus-completion phase, not a transient byte state.
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pub(crate) fn validate(&self, address: u32, bytes: &[u8]) -> Option<(u32, u8, &'static str)> {
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for (offset, &value) in bytes.iter().enumerate() {
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let at = address + offset as u32;
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if let Some(operation) = Self::unsupported(at, value) {
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return Some((at, value, operation));
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}
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}
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let mut next = *self;
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next.merge(address, bytes);
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// Clearing start always permits cancellation/reconfiguration. Other
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// live changes after a shifted bit lack an independently verified model.
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if self.normal() && self.busy() && next.busy() {
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let changed_mode = self.normal() != next.normal();
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let changed_clock = (self.control ^ next.control) & 0x1003 != 0;
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let data_touched = (0..bytes.len()).any(|offset| {
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let at = address + offset as u32;
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if self.width() == 32 {
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(SIODATA32..SIODATA32 + 4).contains(&at)
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} else {
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at == SIODATA8
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}
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});
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if (self.clocked() && changed_mode)
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|| (self.bits_left != self.width()
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&& (changed_clock || changed_mode || data_touched))
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{
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return Some((
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address,
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bytes[0],
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"serial reconfiguration during active transfer",
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));
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}
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}
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None
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}
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fn gpio_pins(&self) -> u16 {
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let outputs = (self.rcnt >> 4) & 15;
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(self.rcnt & outputs & 15) | (!outputs & 15)
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}
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pub(crate) fn read8(&self, address: u32) -> Option<u8> {
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if (SIODATA32..SIODATA32 + 4).contains(&address) {
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return Some(self.data.to_le_bytes()[(address - SIODATA32) as usize]);
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}
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let value = match address & !1 {
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SIOCNT => {
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self.control
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| if self.normal() {
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4
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} else {
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self.gpio_pins() & 4
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}
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}
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SIODATA8 => u16::from(self.send),
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RCNT => {
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if self.normal() && address & 1 == 0 {
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return None;
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}
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(self.rcnt & !15) | self.gpio_pins()
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}
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JOYCNT | JOY_RECV..=0x0400_0156 => 0,
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_ => return None,
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};
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Some(value.to_le_bytes()[(address & 1) as usize])
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}
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fn merge(&mut self, address: u32, bytes: &[u8]) {
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for (offset, &value) in bytes.iter().enumerate() {
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let at = address + offset as u32;
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if (SIODATA32..SIODATA32 + 4).contains(&at) {
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let shift = (at - SIODATA32) * 8;
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self.data = (self.data & !(255 << shift)) | (u32::from(value) << shift);
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} else {
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match at & !1 {
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SIOCNT => self.control = replace_byte(self.control, at, value) & 0x508b,
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SIODATA8 if at & 1 == 0 => self.send = value,
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RCNT => self.rcnt = replace_byte(self.rcnt, at, value) & 0xc1ff,
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_ => {}
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}
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}
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}
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}
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pub(crate) fn write(&mut self, address: u32, bytes: &[u8]) {
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debug_assert!(self.validate(address, bytes).is_none());
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let previous = *self;
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self.merge(address, bytes);
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if !self.normal() || !self.busy() {
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self.bits_left = 0;
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self.until_bit = 0;
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} else if !previous.normal()
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|| !previous.busy()
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|| (previous.control ^ self.control) & 0x1003 != 0
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{
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// New request or an unshifted clock/width change, including external -> internal.
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self.bits_left = self.width();
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self.until_bit = self.period();
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}
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}
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pub(crate) fn next_event_cycles(&self) -> Option<u32> {
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self.clocked()
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.then(|| self.until_bit + u32::from(self.bits_left - 1) * self.period())
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}
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/// At most 32 edges per request. SI is pulled high without a connected partner.
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pub(crate) fn advance(&mut self, mut cycles: u32) -> u16 {
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if !self.clocked() {
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return 0;
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}
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while cycles >= self.until_bit {
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cycles -= self.until_bit;
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if self.width() == 32 {
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self.data = (self.data << 1) | 1;
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} else {
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self.send = (self.send << 1) | 1;
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}
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self.bits_left -= 1;
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if self.bits_left == 0 {
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self.control &= !0x80;
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self.until_bit = 0;
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return if self.control & 0x4000 != 0 { 0x80 } else { 0 };
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}
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self.until_bit = self.period();
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}
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self.until_bit -= cycles;
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0
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}
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}
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@ -1,12 +1,13 @@
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//! Staged timer and audio clocks for one instruction, IRQ entry, or DMA unit.
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//! Staged timer, audio, and serial clocks for one instruction, IRQ entry, or DMA unit.
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//! Other devices remain on the instruction-boundary scheduler.
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use super::{Io, Timer, IF, TIMER_BASE};
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pub(super) const TIMER_IRQ_MASK: u16 = 0x78;
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pub(super) const STAGED_IRQ_MASK: u16 = 0xf8;
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub(crate) struct TimerStep {
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pub(crate) audio: crate::audio::Audio,
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pub(crate) serial: super::Serial,
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pub(super) timers: [Timer; 4],
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pub(super) phase: u16,
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pub(super) pending: u16,
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@ -17,15 +18,17 @@ impl TimerStep {
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pub(super) fn new(io: &Io) -> Self {
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Self {
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audio: io.audio,
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serial: io.serial,
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timers: io.timers,
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phase: io.timer_phase,
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pending: io.pending & TIMER_IRQ_MASK,
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pending: io.pending & STAGED_IRQ_MASK,
|
||||
elapsed: 0,
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) fn advance_to(&mut self, elapsed: u32) {
|
||||
assert!(elapsed >= self.elapsed, "timer step time must be monotonic");
|
||||
self.pending |= self.serial.advance(elapsed - self.elapsed);
|
||||
self.pending |= Io::advance_timer_bank(
|
||||
&mut self.timers,
|
||||
&mut self.phase,
|
||||
|
|
@ -44,7 +47,7 @@ impl TimerStep {
|
|||
TIMER_BASE..=0x0400_010f => {
|
||||
Some(self.timers[((address - TIMER_BASE) / 4) as usize].read8(address))
|
||||
}
|
||||
IF => Some((committed & !(TIMER_IRQ_MASK as u8)) | self.pending as u8),
|
||||
IF => Some((committed & !(STAGED_IRQ_MASK as u8)) | self.pending as u8),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
|
@ -59,7 +62,7 @@ impl TimerStep {
|
|||
}
|
||||
IF => {
|
||||
self.pending &= !u16::from(value);
|
||||
false // The normal I/O path must also acknowledge non-timer sources.
|
||||
false // The normal I/O path must also acknowledge non-staged sources.
|
||||
}
|
||||
_ => false,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ impl Machine {
|
|||
/// Sample IRQ before executing the next instruction. GBA devices do not
|
||||
/// generate FIQ. IRQ entry consumes a separate step and does not clear IF.
|
||||
/// CPU/DMA work uses nominal costs; HALT advances exactly to the next device event.
|
||||
/// Timer data accesses use staged bus-completion phases. Other device writes
|
||||
/// Timer, sound, and serial accesses use staged bus-completion phases. Other device writes
|
||||
/// precede their bulk clock update. IRQ synchronization delays are not modeled. Opcode
|
||||
/// prefetch follows ordered nominal CPU/DMA costs, not per-cycle arbitration.
|
||||
/// CPU/DMA diagnostics leave CPU, devices, and the clock unchanged for this step.
|
||||
|
|
|
|||
|
|
@ -13,6 +13,8 @@ mod iwram_history_tests;
|
|||
#[cfg(test)]
|
||||
mod prefetch_tests;
|
||||
#[cfg(test)]
|
||||
mod serial_step_tests;
|
||||
#[cfg(test)]
|
||||
mod timer_step_tests;
|
||||
#[cfg(test)]
|
||||
mod timing_event_tests;
|
||||
|
|
@ -25,7 +27,7 @@ use crate::{
|
|||
display::{DisplayPosition, CYCLES_PER_LINE, HBLANK_START, VISIBLE_LINES},
|
||||
dma::{DmaError, DMA_BASE, DMA_END},
|
||||
input::Buttons,
|
||||
io::{Io, TimerStep, HALTCNT, KEYINPUT, POSTFLG},
|
||||
io::{Io, Serial, TimerStep, HALTCNT, KEYINPUT, POSTFLG},
|
||||
timing::{AccessKind, AccessWidth, CpuTiming, Prefetch, StepTiming},
|
||||
video::{self, sprites::pipeline, Framebuffer, VideoError},
|
||||
};
|
||||
|
|
@ -107,7 +109,7 @@ struct CpuAccess {
|
|||
/// Successful DMA accesses drive local lanes even before the first CPU instruction.
|
||||
/// Channel data remains separate; general and sub-instruction CPU bus handoff is unmodeled.
|
||||
/// Instruction buffering and supported bus history consume shared fetch samples.
|
||||
/// Timer and sound accesses use staged machine-step time; other per-access device timing remains unmodeled.
|
||||
/// Timer, sound, and serial accesses use staged machine-step time; other per-access device timing remains unmodeled.
|
||||
pub struct Memory {
|
||||
external_ram: Vec<u8>,
|
||||
internal_ram: Vec<u8>,
|
||||
|
|
@ -177,6 +179,12 @@ impl Memory {
|
|||
self.io.audio.level()
|
||||
}
|
||||
|
||||
fn serial_state(&self) -> Serial {
|
||||
self.timer_step
|
||||
.get()
|
||||
.map_or(self.io.serial, |step| step.serial)
|
||||
}
|
||||
|
||||
fn audio_state(&self) -> Audio {
|
||||
self.timer_step
|
||||
.get()
|
||||
|
|
@ -231,7 +239,7 @@ impl Memory {
|
|||
.take()
|
||||
.expect("machine timer transaction is active");
|
||||
self.io.commit_timer_step(step);
|
||||
// Timers already reached this boundary. Advance other devices exactly once.
|
||||
// Staged devices already reached this boundary. Advance remaining devices exactly once.
|
||||
self.advance_running_cycles_with_timers(cycles, false);
|
||||
}
|
||||
|
||||
|
|
@ -258,7 +266,7 @@ impl Memory {
|
|||
self.io.advance(cycles - advanced, advance_timers);
|
||||
} else {
|
||||
// Split at display and sprite-preparation edges. Video writes have
|
||||
// already committed. Machine timer transactions skip this bulk timer clock.
|
||||
// already committed. Staged devices skip their bulk clock on machine steps.
|
||||
let mut remaining = cycles;
|
||||
while remaining != 0 {
|
||||
let position = self.io.display_position();
|
||||
|
|
@ -689,6 +697,12 @@ impl Memory {
|
|||
fn read_byte(&self, address: u32) -> Result<u8, MemoryError> {
|
||||
if address >> 24 == 0x04 {
|
||||
if let Some(step) = self.timer_step.get() {
|
||||
if Serial::mapped(address) {
|
||||
return step
|
||||
.serial
|
||||
.read8(address)
|
||||
.ok_or(MemoryError::Unmapped(address));
|
||||
}
|
||||
if let Some(value) = step.read8(address, self.io.read8(address).unwrap_or(0)) {
|
||||
return Ok(value);
|
||||
}
|
||||
|
|
@ -798,6 +812,18 @@ impl Memory {
|
|||
self.iwram_bus.access(address, width, value);
|
||||
}
|
||||
if address >> 24 == 0x04 {
|
||||
if Serial::mapped(address) {
|
||||
let mut serial = self.serial_state();
|
||||
Self::validate_serial(&serial, address, &bytes)?;
|
||||
serial.write(address, &bytes);
|
||||
if let Some(mut step) = self.timer_step.get() {
|
||||
step.serial = serial;
|
||||
self.timer_step.set(Some(step));
|
||||
} else {
|
||||
self.io.serial = serial;
|
||||
}
|
||||
return Ok(());
|
||||
}
|
||||
if Audio::mapped(address) {
|
||||
if let Some(mut step) = self.timer_step.get() {
|
||||
step.audio.write(address, &bytes);
|
||||
|
|
@ -930,15 +956,49 @@ impl Memory {
|
|||
Ok(())
|
||||
}
|
||||
|
||||
fn validate_serial(serial: &Serial, address: u32, bytes: &[u8]) -> Result<(), MemoryError> {
|
||||
if let Some((address, value, operation)) = serial.validate(address, bytes) {
|
||||
return Err(MemoryError::UnsupportedIo {
|
||||
address,
|
||||
value,
|
||||
operation,
|
||||
});
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Validate a batch before any RAM or I/O writes. Diagnostic errors cannot
|
||||
/// leave a partial block store. This is not a model of hardware data aborts.
|
||||
/// Mapped I/O reads currently have no side effects; writes cannot fail after validation.
|
||||
pub(crate) fn write_words(&mut self, writes: &[(u32, u32)]) -> Result<(), MemoryError> {
|
||||
let mut audio = self.audio_state();
|
||||
for &(address, value) in writes {
|
||||
self.write_index::<4>(address, self.write_access())?;
|
||||
Self::validate_io_values(&mut audio, address, &value.to_le_bytes())?;
|
||||
}
|
||||
let mut serial = self.serial_state();
|
||||
let timing = self.cpu_timing.get();
|
||||
let devices = self.timer_step.get();
|
||||
// Preflight ordered data phases on temporary device/timing copies.
|
||||
// A serial request can finish before a later control write reaches the bus.
|
||||
let validation = (|| {
|
||||
for &(address, value) in writes {
|
||||
self.write_index::<4>(address, self.write_access())?;
|
||||
let bytes = value.to_le_bytes();
|
||||
Self::validate_io_values(&mut audio, address, &bytes)?;
|
||||
self.record_access(address, AccessWidth::Word);
|
||||
if Serial::mapped(address) {
|
||||
if let Some(mut step) = self.timer_step.get() {
|
||||
Self::validate_serial(&step.serial, address, &bytes)?;
|
||||
step.serial.write(address, &bytes);
|
||||
self.timer_step.set(Some(step));
|
||||
} else {
|
||||
Self::validate_serial(&serial, address, &bytes)?;
|
||||
serial.write(address, &bytes);
|
||||
}
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
})();
|
||||
self.cpu_timing.set(timing);
|
||||
self.timer_step.set(devices);
|
||||
validation?;
|
||||
for &(address, value) in writes {
|
||||
// The map cannot change between validation and these writes.
|
||||
self.write32(address, value)?;
|
||||
|
|
|
|||
214
crates/gba-core/src/memory/serial_step_tests.rs
Normal file
214
crates/gba-core/src/memory/serial_step_tests.rs
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
//! Serial progress belongs to the same speculative bus phases as timers/audio.
|
||||
use super::{timing_event_tests::prepared, *};
|
||||
use crate::{
|
||||
io::{IF, RCNT, SIOCNT, SIODATA8, SOUNDCNT_X},
|
||||
machine::{Machine, StepKind},
|
||||
};
|
||||
|
||||
fn start(memory: &mut Memory, elapsed: u32) {
|
||||
memory.write16(SIOCNT, 0x4083).unwrap(); // 8 bits, eight cycles per bit.
|
||||
memory.advance_cycles(elapsed);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn cpu_starts_at_data_completion_and_cpu_only_execution_does_not_shift() {
|
||||
for (thumb, instruction) in [(false, 0xe1c100b0), (true, 0x8008)] {
|
||||
// STRH r0,[r1]
|
||||
let (mut cpu, mut memory) = prepared(thumb, &[instruction], &[(0, 0x4083), (1, SIOCNT)]);
|
||||
cpu.step_timed(&mut memory).unwrap();
|
||||
let started = memory.io.serial;
|
||||
assert_eq!(started.next_event_cycles(), Some(64));
|
||||
let (cpu, memory) = prepared(thumb, &[instruction], &[(0, 0x4083), (1, SIOCNT)]);
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.memory().io.serial, started); // No preceding fetch/data cycles charged to the new request.
|
||||
assert_eq!(machine.last_timing().data_cycles, 1);
|
||||
machine.memory_mut().advance_cycles(63);
|
||||
assert_eq!(machine.memory().read8(SIODATA8).unwrap(), 0x7f);
|
||||
machine.memory_mut().advance_cycles(1);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0x80);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn arm_and_thumb_loads_sample_before_the_trailing_internal_cycle() {
|
||||
for (thumb, instruction, elapsed) in [(false, 0xe1d100b0, 56), (true, 0x8808, 59)] {
|
||||
let (cpu, mut memory) = prepared(thumb, &[instruction], &[(1, SIOCNT)]);
|
||||
start(&mut memory, elapsed);
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.cpu().registers()[0], 0x4087);
|
||||
assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x4007);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0x80);
|
||||
assert_eq!(machine.cycles(), 64);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn if_acknowledgement_at_the_completion_phase_clears_serial_but_not_other_sources() {
|
||||
let (cpu, mut memory) = prepared(false, &[0xe1c100b0], &[(0, 0x80), (1, IF)]);
|
||||
start(&mut memory, 57);
|
||||
memory.write16(crate::io::KEYCNT, 0x4001).unwrap();
|
||||
memory.set_buttons(crate::input::Buttons::from_bits(1));
|
||||
assert_eq!(memory.read16(IF).unwrap(), 0x1000);
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
machine.step().unwrap(); // Fetch six cycles + one data cycle: complete, then acknowledge.
|
||||
assert_eq!(machine.cycles(), 64);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0x1000);
|
||||
assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x4007);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn single_and_block_store_validation_uses_completion_phase_and_does_not_double_advance() {
|
||||
for instruction in [0xe5810000, 0xe8a10001] {
|
||||
// STR and STMIA r1!,{r0}
|
||||
for elapsed in [56, 57] {
|
||||
let (cpu, mut memory) =
|
||||
prepared(false, &[instruction], &[(0, 0x00204081), (1, SIOCNT)]);
|
||||
start(&mut memory, elapsed);
|
||||
let serial = memory.io.serial;
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
let cpu = machine.cpu().clone();
|
||||
if elapsed == 57 {
|
||||
machine.step().unwrap(); // Previous request completes at this write's phase.
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0x80);
|
||||
assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x4085);
|
||||
assert_eq!(machine.memory().read8(SIODATA8).unwrap(), 0x20);
|
||||
assert_eq!(machine.memory().io.serial.next_event_cycles(), Some(512));
|
||||
assert_eq!(machine.cycles(), 64);
|
||||
} else {
|
||||
let error = machine.step().unwrap_err();
|
||||
assert!(error.to_string().contains("serial reconfiguration"));
|
||||
assert_eq!(machine.step(), Err(error));
|
||||
assert_eq!(machine.cpu(), &cpu);
|
||||
assert_eq!(machine.cycles(), u64::from(elapsed));
|
||||
assert_eq!(machine.memory().io.serial, serial);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0);
|
||||
}
|
||||
assert!(machine.memory().timer_step.get().is_none());
|
||||
assert!(machine.memory().cpu_timing.get().is_none());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn later_block_failure_restores_completion_and_partial_serial_writes() {
|
||||
let (cpu, mut memory) = prepared(
|
||||
false,
|
||||
&[0xe8a10005],
|
||||
&[(0, 0x00204081), (1, SIOCNT), (2, 0)],
|
||||
);
|
||||
start(&mut memory, 57);
|
||||
let serial = memory.io.serial;
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
let cpu = machine.cpu().clone();
|
||||
for _ in 0..2 {
|
||||
assert!(machine
|
||||
.step()
|
||||
.unwrap_err()
|
||||
.to_string()
|
||||
.contains("0x0400012c"));
|
||||
assert_eq!(machine.memory().io.serial, serial);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0);
|
||||
assert_eq!(machine.cpu(), &cpu);
|
||||
assert_eq!(machine.cycles(), 57);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn dma_source_observes_old_busy_then_destination_phase_commits_completion() {
|
||||
let (cpu, mut memory) = prepared(false, &[0xe1a00000], &[]);
|
||||
start(&mut memory, 60);
|
||||
memory.write32(DMA_BASE, SIOCNT).unwrap();
|
||||
memory.write32(DMA_BASE + 4, 0x02000000).unwrap();
|
||||
memory.write32(DMA_BASE + 8, 0xc4000001).unwrap();
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 0 });
|
||||
assert_eq!(machine.memory().read32(0x02000000).unwrap(), 0x007f4087);
|
||||
assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x4007);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0x180); // Both sources survive their separate commits.
|
||||
assert_eq!(machine.cycles(), 69);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn dma_start_excludes_source_cycles_and_failed_destination_discards_serial_progress() {
|
||||
for fail in [false, true] {
|
||||
let (cpu, mut memory) = prepared(false, &[0xe1a00000], &[]);
|
||||
if fail {
|
||||
start(&mut memory, 60);
|
||||
memory.write16(SOUNDCNT_X, 0x80).unwrap();
|
||||
}
|
||||
memory
|
||||
.write32(0x02000000, if fail { 0x8000 } else { 0x4083 })
|
||||
.unwrap();
|
||||
memory.write32(DMA_BASE, 0x02000000).unwrap();
|
||||
memory
|
||||
.write32(DMA_BASE + 4, if fail { 0x04000074 } else { SIOCNT })
|
||||
.unwrap();
|
||||
memory.write32(DMA_BASE + 8, 0x84000001).unwrap();
|
||||
let serial = memory.io.serial;
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
if fail {
|
||||
let cpu = machine.cpu().clone();
|
||||
let error = machine.step().unwrap_err();
|
||||
assert_eq!(machine.step(), Err(error));
|
||||
assert_eq!(machine.memory().io.serial, serial);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0);
|
||||
assert_eq!(machine.cpu(), &cpu);
|
||||
assert_eq!(machine.cycles(), 60);
|
||||
} else {
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.cycles(), 9);
|
||||
assert_eq!(machine.memory().io.serial.next_event_cycles(), Some(64));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn batch_validation_carries_control_changes_without_committing_earlier_ram_on_error() {
|
||||
let (_, mut memory) = prepared(false, &[0xe1a00000], &[]);
|
||||
start(&mut memory, 8);
|
||||
let serial = memory.io.serial;
|
||||
assert!(memory
|
||||
.write_words(&[(0x02000000, 0x12345678), (SIOCNT, 0x00aa4083)])
|
||||
.is_err());
|
||||
assert_eq!(memory.read32(0x02000000).unwrap(), 0);
|
||||
assert_eq!(memory.io.serial, serial);
|
||||
memory
|
||||
.write_words(&[(SIOCNT, 0), (SIOCNT, 0x00aa4083)])
|
||||
.unwrap();
|
||||
assert_eq!(memory.read8(SIODATA8).unwrap(), 0xaa);
|
||||
assert_eq!(memory.io.serial.next_event_cycles(), Some(64));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn staged_unmapped_pin_reads_do_not_fall_back_to_old_committed_gpio_state() {
|
||||
let (_, mut memory) = prepared(false, &[0xe1a00000], &[]);
|
||||
memory.write16(RCNT, 0x8000).unwrap();
|
||||
memory.begin_timer_step();
|
||||
memory.write16(RCNT, 0).unwrap();
|
||||
assert_eq!(memory.read8(RCNT), Err(MemoryError::Unmapped(RCNT)));
|
||||
memory.discard_timer_step();
|
||||
assert_eq!(memory.read16(RCNT).unwrap(), 0x800f);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn capture_splits_and_cpu_clock_commits_do_not_duplicate_serial_edges() {
|
||||
let (cpu, mut plain) = prepared(false, &[0xe1a00000; 100], &[]);
|
||||
let (_, mut captured) = prepared(false, &[0xe1a00000; 100], &[]);
|
||||
plain.advance_cycles(950);
|
||||
captured.advance_cycles(950);
|
||||
captured.set_scanline_rendering(true);
|
||||
start(&mut plain, 0);
|
||||
start(&mut captured, 0);
|
||||
let mut plain = Machine::new(cpu.clone(), plain);
|
||||
let mut captured = Machine::new(cpu, captured);
|
||||
for _ in 0..20 {
|
||||
plain.step().unwrap();
|
||||
captured.step().unwrap();
|
||||
assert_eq!(plain.memory().io.serial, captured.memory().io.serial);
|
||||
assert_eq!(plain.memory().read16(IF), captured.memory().read16(IF));
|
||||
assert_eq!(plain.cycles(), captured.cycles());
|
||||
}
|
||||
assert_eq!(plain.memory().read8(SIODATA8).unwrap(), 0xff);
|
||||
}
|
||||
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Add table
Add a link
Reference in a new issue