feat(cpu): charge non-refill code at pipeline fetch addresses
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26 changed files with 413 additions and 46 deletions
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@ -45,6 +45,7 @@ Update this file when a feature lands or a limit is removed.
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- STOP freezes CPU/DMA/device clocks, retains device phases, and reports a stopped frame runner without spinning.
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- Machine execution to the next VBlank event, with a configurable step limit.
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- CPU/device stepping with nominal ARM7 instruction costs and memory wait states.
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- Non-refill code costs use actual ARM PC+8/Thumb PC+4 fetch addresses, including memory-region and ROM wait-window boundaries.
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- Game Pak wait-state control (`WAITCNT`) for all three ROM windows.
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- Sequential/non-sequential data accesses, branch refill costs, and variable multiply timing.
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- Optional caller-supplied 16 KiB BIOS mapping, with CPU read protection based on retained ARM PC+8 or aligned Thumb PC+4 words.
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@ -161,7 +162,8 @@ Writes to cartridge addresses return errors instead of modeling cartridge hardwa
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Keep unknown history diagnostic until fetch ordering and latch ownership have independent coverage.
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Validate BIOS snapshots with independent hardware tests before claiming exact refill or data-access history.
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The desktop runner still uses only the original BIOS. Keep protected reads image-derived for all supplied images.
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2. Connect instruction buffering to fetch timing, Game Pak prefetch, per-access device updates, and verified timer/IRQ delays.
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2. Replace destination-only refill summaries with verified source-fetch/target-pair timing, including IRQ entry.
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Then extend access-kind sequencing, startup costs, Game Pak prefetch, per-access device updates, and timer/IRQ delays.
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3. Validate keypad retrigger behavior with hardware tests and add remaining device registers; extend BIOS reset coverage as sound/serial support becomes available.
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Validate STOP entry/wake edges and add external wake sources and remaining DMA device modes.
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4. Replace nominal sprite work limits with verified individual fetch timing; add background fetch timing and per-pixel composition.
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