feat(bios): add original boot IRQ waits and memory services
Generate original ARM firmware for minimal boot, IRQ callbacks, HALT, IntrWait, CpuSet, and CpuFastSet.
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321
src/bios.rs
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321
src/bios.rs
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//! Original, optional ARM BIOS replacement. No Nintendo firmware is included.
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//! Supports interrupt waits and memory copy/fill.
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//! This is a functional subset, not a complete boot ROM or a timing-compatible BIOS.
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use std::collections::BTreeMap;
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use crate::{
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cpu::Cpu,
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io::{HALTCNT, IME, POSTFLG},
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machine::Machine,
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memory::{Memory, MemoryError, BIOS_SIZE, ROM_START},
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};
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pub const SYSTEM_STACK: u32 = 0x0300_7f00;
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pub const IRQ_STACK: u32 = 0x0300_7fa0;
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pub const SVC_STACK: u32 = 0x0300_7fe0;
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pub const IRQ_FLAGS: u32 = 0x0300_7ff8;
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pub const IRQ_HANDLER: u32 = 0x0300_7ffc;
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/// An intentional undefined instruction used for unsupported SWIs/vectors and invalid IRQ pointers.
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pub const UNSUPPORTED_TRAP: u32 = 0xe7f0_00f0;
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/// A separate diagnostic trap for division by zero or invalid unpacking/decompression arguments.
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pub const INVALID_ARGUMENT_TRAP: u32 = 0xe7f0_00f1;
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/// Start at reset with our optional firmware. Call Machine::step to execute boot.
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/// Boot initializes three stacks, POSTFLG, and the IRQ communication words, then
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/// enters ROM_START in ARM System mode. It does not validate a cartridge header,
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/// reproduce Nintendo's boot process, or provide file loading.
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pub fn boot(rom: Vec<u8>) -> Result<Machine, MemoryError> {
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Ok(Machine::new(
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Cpu::at_reset(),
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Memory::with_bios(rom, image())?,
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))
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}
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/// Build a deterministic 16 KiB image from original ARM instructions.
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/// SWIs use bits 16–23 of the ARM immediate, or the Thumb immediate byte.
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/// Services support User/System callers and preserve caller status. Registers
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/// other than each arithmetic service's documented outputs are preserved.
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/// IRQ callbacks must preserve r4–r11, acknowledge IF, update IRQ_FLAGS for wait
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/// services, and return with BX lr. Nested IRQs and SWIs from callbacks are unsupported.
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/// Service routines use the Supervisor stack; exact firmware stack layout and
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/// undocumented BIOS side effects are not reproduced.
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pub fn image() -> Vec<u8> {
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let mut a = ArmImage::default();
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for vector in [
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"reset",
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"unsupported",
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"swi",
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"unsupported",
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"unsupported",
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"unsupported",
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"irq",
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"unsupported",
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] {
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a.branch(14, vector);
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}
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a.label("reset");
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a.emit(0xe321_f0d3); // MSR CPSR_c,#SVC|I|F
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a.literal(13, SVC_STACK);
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a.emit(0xe321_f0d2); // MSR CPSR_c,#IRQ|I|F
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a.literal(13, IRQ_STACK);
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a.emit(0xe321_f0df); // MSR CPSR_c,#System|I|F
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a.literal(13, SYSTEM_STACK);
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a.emit(0xe3a0_0000); // MOV r0,#0
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a.literal(1, IRQ_FLAGS);
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a.emit(0xe581_0000); // STR r0,[r1] (flags and reserved upper halfword)
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a.emit(0xe581_0004); // STR r0,[r1,#4] (callback pointer)
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a.literal(1, IME);
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a.emit(0xe581_0000); // STR r0,[r1] (disable IRQ delivery during minimal boot)
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a.literal(1, POSTFLG);
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a.emit(0xe3a0_0001); // MOV r0,#1
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a.emit(0xe5c1_0000); // STRB r0,[r1]
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a.emit(0xe321_f01f); // MSR CPSR_c,#System
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a.literal(15, ROM_START); // LDR pc,=ROM_START
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a.label("irq");
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a.emit(0xe92d_500f); // STMDB sp!,{r0-r3,r12,lr}
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a.literal(1, IRQ_HANDLER);
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a.emit(0xe591_1000); // LDR r1,[r1]
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a.emit(0xe351_0000); // CMP r1,#0
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a.branch(0, "unsupported");
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a.emit(0xe311_0003); // TST r1,#3 (hardware callback is word-aligned ARM)
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a.branch(1, "unsupported");
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a.emit(0xe3a0_0301); // MOV r0,#0x04000000 (callback convention)
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a.emit(0xe1a0_e00f); // MOV lr,pc (return after BX)
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a.emit(0xe12f_ff11); // BX r1
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a.emit(0xe8bd_500f); // LDMIA sp!,{r0-r3,r12,lr}
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a.emit(0xe25e_f004); // SUBS pc,lr,#4
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a.label("swi");
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a.emit(0xe92d_500f); // STMDB sp!,{r0-r3,r12,lr}
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a.emit(0xe14f_3000); // MRS r3,SPSR
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a.emit(0xe92d_0008); // STMDB sp!,{r3} (save caller status across IRQs)
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// Keep stack usage bounded within the default 64-byte Supervisor area.
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// In particular, reject a nested SWI from an IRQ callback during a wait.
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a.emit(0xe203_c01f); // AND r12,r3,#mode mask
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a.emit(0xe35c_0010); // CMP r12,#User
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a.branch(0, "decode_swi");
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a.emit(0xe35c_001f); // CMP r12,#System
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a.branch(1, "unsupported");
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a.label("decode_swi");
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a.emit(0xe313_0020); // TST r3,#Thumb
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a.emit(0x115e_c0b2); // LDRHNE r12,[lr,#-2]
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a.emit(0x051e_c004); // LDREQ r12,[lr,#-4]
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a.emit(0x01a0_c82c); // MOVEQ r12,r12,LSR #16
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a.emit(0xe20c_c0ff); // AND r12,r12,#0xff
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for (number, target) in [
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(2, "halt"),
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(4, "intr_wait"),
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(5, "vblank_wait"),
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(0x0b, "cpu_set"),
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(0x0c, "cpu_fast_set"),
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] {
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a.emit(0xe35c_0000 | number); // CMP r12,#service
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a.branch(0, target);
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}
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a.branch(14, "unsupported");
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a.label("halt");
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a.literal(1, HALTCNT);
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a.emit(0xe3a0_0000); // MOV r0,#0
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a.emit(0xe5c1_0000); // STRB r0,[r1]
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a.branch(14, "return");
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a.label("vblank_wait");
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a.emit(0xe3a0_0001); // MOV r0,#1 (discard old flags)
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a.emit(0xe3a0_1001); // MOV r1,#VBlank
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a.label("intr_wait");
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a.literal(12, IME);
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a.emit(0xe3a0_3001); // MOV r3,#1
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a.emit(0xe58c_3000); // STR r3,[r12] (IME=1)
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a.literal(2, IRQ_FLAGS);
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a.emit(0xe350_0000); // CMP r0,#0
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a.branch(0, "wait_unmask");
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a.emit(0xe1d2_30b0); // LDRH r3,[r2]
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a.emit(0xe1c3_3001); // BIC r3,r3,r1
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a.emit(0xe1c2_30b0); // STRH r3,[r2]
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a.label("wait_unmask");
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a.emit(0xe10f_3000); // MRS r3,CPSR
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a.emit(0xe3c3_3080); // BIC r3,r3,#I
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a.emit(0xe121_f003); // MSR CPSR_c,r3
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a.label("wait_loop");
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// Mask IME while checking flags and entering HALT. A new hardware request
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// still wakes HALT, but cannot be acknowledged between the check and sleep.
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a.emit(0xe3a0_3000); // MOV r3,#0
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a.emit(0xe58c_3000); // STR r3,[r12] (IME=0)
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a.emit(0xe1d2_30b0); // LDRH r3,[r2]
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a.emit(0xe113_0001); // TST r3,r1
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a.branch(1, "wait_done");
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a.literal(0, HALTCNT);
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a.emit(0xe3a0_3000); // MOV r3,#0
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a.emit(0xe5c0_3000); // STRB r3,[r0] (HALT)
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a.emit(0xe3a0_3001); // MOV r3,#1
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a.emit(0xe58c_3000); // STR r3,[r12] (IME=1, allow IRQ callback to record flags)
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a.branch(14, "wait_loop");
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a.label("wait_done");
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a.emit(0xe1c3_3001); // BIC r3,r3,r1 (consume selected flags only)
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a.emit(0xe1c2_30b0); // STRH r3,[r2]
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a.emit(0xe3a0_3001); // MOV r3,#1
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a.emit(0xe58c_3000); // STR r3,[r12]
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a.branch(14, "return");
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a.label("cpu_set");
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emit_count(&mut a);
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a.emit(0xe312_0301); // TST r2,#0x04000000 (word width)
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a.branch(1, "copy_word");
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a.branch(14, "copy_halfword");
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a.label("cpu_fast_set");
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emit_count(&mut a);
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a.emit(0xe283_3007); // ADD r3,r3,#7
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a.emit(0xe3c3_3007); // BIC r3,r3,#7 (round up to eight words)
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emit_copy_checks(&mut a, true);
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a.emit(0xe92d_0ff0); // STMDB sp!,{r4-r11} (60 bytes total SVC stack use)
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a.emit(0xe312_0401); // TST r2,#0x01000000
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a.branch(0, "fast_copy_loop");
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a.emit(0xe590_4000); // LDR r4,[r0] (read fill value once)
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for register in 5..=11 {
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a.emit(0xe1a0_0004 | register << 12);
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} // MOV rN,r4
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a.label("fast_fill_loop");
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a.emit(0xe8a1_0ff0); // STMIA r1!,{r4-r11}
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a.emit(0xe253_3008); // SUBS r3,r3,#8
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a.branch(1, "fast_fill_loop");
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a.branch(14, "fast_done");
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a.label("fast_copy_loop");
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a.emit(0xe8b0_0ff0); // LDMIA r0!,{r4-r11}
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a.emit(0xe8a1_0ff0); // STMIA r1!,{r4-r11}
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a.emit(0xe253_3008); // SUBS r3,r3,#8
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a.branch(1, "fast_copy_loop");
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a.label("fast_done");
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a.emit(0xe8bd_0ff0); // LDMIA sp!,{r4-r11}
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a.branch(14, "return");
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emit_copy(
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&mut a,
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true,
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["copy_word", "word_loop", "word_fill", "word_fill_loop"],
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);
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emit_copy(
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&mut a,
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false,
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["copy_halfword", "half_loop", "half_fill", "half_fill_loop"],
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);
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a.label("return");
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a.emit(0xe10f_3000); // MRS r3,CPSR
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a.emit(0xe383_3080); // ORR r3,r3,#I (protect status/stack restoration)
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a.emit(0xe121_f003); // MSR CPSR_c,r3
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a.emit(0xe8bd_0008); // LDMIA sp!,{r3}
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a.emit(0xe169_f003); // MSR SPSR_fc,r3
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a.emit(0xe8bd_500f); // LDMIA sp!,{r0-r3,r12,lr}
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a.emit(0xe1b0_f00e); // MOVS pc,lr
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a.label("unsupported");
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a.emit(UNSUPPORTED_TRAP);
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a.label("invalid_argument");
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a.emit(INVALID_ARGUMENT_TRAP);
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a.finish()
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}
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fn emit_count(a: &mut ArmImage) {
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a.emit(0xe1a0_3582); // MOV r3,r2,LSL #11
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a.emit(0xe1a0_35a3); // MOV r3,r3,LSR #11 (low 21 bits)
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}
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fn emit_copy_checks(a: &mut ArmImage, word: bool) {
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a.emit(0xe353_0000); // CMP r3,#0
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a.branch(0, "return");
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a.emit(if word { 0xe3c0_0003 } else { 0xe3c0_0001 }); // BIC r0,r0,#alignment mask
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a.emit(if word { 0xe3c1_1003 } else { 0xe3c1_1001 }); // BIC r1,r1,#alignment mask
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// Reject protected source ranges and wrapping end addresses before writing.
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a.emit(0xe350_0402); // CMP r0,#0x02000000
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a.branch(3, "return"); // BLO
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a.emit(if word { 0xe090_c103 } else { 0xe090_c083 }); // ADDS r12,r0,r3,LSL #2/#1
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a.branch(2, "return"); // BCS (address overflow)
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a.emit(0xe35c_0402); // CMP r12,#0x02000000
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a.branch(3, "return");
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}
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fn emit_copy(a: &mut ArmImage, word: bool, labels: [&'static str; 4]) {
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let [entry, copy_loop, fill, fill_loop] = labels;
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a.label(entry);
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emit_copy_checks(a, word);
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a.emit(0xe312_0401); // TST r2,#0x01000000 (fixed source)
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a.branch(1, fill);
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a.label(copy_loop);
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a.emit(if word { 0xe490_2004 } else { 0xe0d0_20b2 }); // LDR/LDRH r2,[r0],#width
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a.emit(if word { 0xe481_2004 } else { 0xe0c1_20b2 }); // STR/STRH r2,[r1],#width
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a.emit(0xe253_3001); // SUBS r3,r3,#1
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a.branch(1, copy_loop);
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a.branch(14, "return");
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a.label(fill);
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a.emit(if word { 0xe590_2000 } else { 0xe1d0_20b0 }); // Read fixed source once.
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a.label(fill_loop);
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a.emit(if word { 0xe481_2004 } else { 0xe0c1_20b2 });
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a.emit(0xe253_3001);
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a.branch(1, fill_loop);
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a.branch(14, "return");
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}
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/// Small image builder for branch/literal fixups. Not a general ARM assembler.
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#[derive(Default)]
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struct ArmImage {
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code: Vec<u32>,
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labels: BTreeMap<&'static str, usize>,
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branches: Vec<(usize, u32, &'static str, bool)>,
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literals: Vec<(usize, u32, u32)>,
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}
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impl ArmImage {
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fn emit(&mut self, instruction: u32) {
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self.code.push(instruction);
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}
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fn label(&mut self, name: &'static str) {
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assert!(
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self.labels.insert(name, self.code.len()).is_none(),
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"duplicate BIOS label"
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);
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}
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fn branch(&mut self, condition: u32, target: &'static str) {
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self.branches
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.push((self.code.len(), condition, target, false));
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self.emit(0);
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}
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fn call(&mut self, target: &'static str) {
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self.branches.push((self.code.len(), 14, target, true));
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self.emit(0);
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}
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fn literal(&mut self, register: u32, value: u32) {
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self.literals.push((self.code.len(), register, value));
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self.emit(0);
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}
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fn finish(mut self) -> Vec<u8> {
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for (index, condition, target, link) in self.branches {
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let offset = self.labels[target] as i32 - index as i32 - 2;
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assert!((-0x80_0000..0x80_0000).contains(&offset));
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self.code[index] = condition << 28
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| 0x0a00_0000
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| (u32::from(link) << 24)
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| (offset as u32 & 0x00ff_ffff);
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}
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for (index, register, value) in self.literals {
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let offset = (self.code.len() as i32 - index as i32 - 2) * 4;
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assert!(offset.unsigned_abs() <= 0xfff);
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self.code[index] = (if offset < 0 { 0xe51f_0000 } else { 0xe59f_0000 })
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| register << 12
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| offset.unsigned_abs();
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self.code.push(value);
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}
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let mut bytes: Vec<u8> = self.code.into_iter().flat_map(u32::to_le_bytes).collect();
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assert!(bytes.len() <= BIOS_SIZE);
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bytes.resize(BIOS_SIZE, 0);
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bytes
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}
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}
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